ZL30402/QCC ZARLINK [Zarlink Semiconductor Inc], ZL30402/QCC Datasheet - Page 19

• Manufacturer Part Number: ZL30402/QCC
• Description: SONET/SDH Network Element PLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 01 H
Address: 04 H
Bit
5-0
Bit
7
6
5
4
3
2
1
0
7
6
HOLDOVER
E3DS3/OC3
Name
LOCK
FLIM
RSV
RSV
RSV
RSV
RSV
E3/DS3
Name
RSV
Reserved.
Reserved.
Lock. This bit goes high when the Core PLL is locked to the selected Acquisition
PLL.
Holdover. This bit goes high when the Core PLL enters Holdover mode. Detection
of reference failure and subsequent transition from Normal to Holdover state takes
approximately: 0.750 µs for 19.44 MHz reference, 0.850 µs for 2.048 MHz
reference, 1.1 µs for 1.544 MHz reference and 130 µs for 8 kHz reference.
Reserved.
Frequency Limit. This bit goes high when the Core PLL is pulled by the input
reference signal to the edge of its frequency tracking range set at ±104 ppm. This
bit may change state momentarily in the event of large jitter or wander excursions
occurring when the input reference is close to the frequency limit range.
Reserved.
Reserved.
E3, DS3 or OC-3 clock select. Setting this bit to zero enables the
C155P/N outputs (pin 30 and pin 31) and enables the C34/C44 output
(pin 53) to provide C8 or C11 clocks. Logic high sets the C155 clock
outputs into high impedance and enables the C34/C44 output to
provide a C34 or C44 clock.
E3 or DS3 clock select. When E3DS3/OC3 bit is set high, a logic
low on the E3/DS3 bit selects a 44.736 MHz clock on the C34/C44
output and logic high selects a 34.368 MHz clock. When the
E3DS3/OC3 bit is set low, a logic low on the E3/DS3 bit selects an
11.184 MHz clock on the C34/C44 output and a logic high selects
an 8.592 MHz clock.
Reserved.
Table 7 - Control Register 2 (R/W)
Table 6 - Status Register 1 (R)
Zarlink Semiconductor Inc.
ZL30402
Functional Description
19
Functional Description
Data Sheet
Default
000000
0
0