ZL30402/QCC ZARLINK [Zarlink Semiconductor Inc], ZL30402/QCC Datasheet - Page 24

• Manufacturer Part Number: ZL30402/QCC
• Description: SONET/SDH Network Element PLL
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Address: 28 H
Address: 40 H
Address: 41 H
Address: 42 H
7-5
4-3
Bit
7-0
Bit
2
1
0
7-0
7-0
Bit
Bit
InpFreq1-0
MCFC31 - 24
Name
SAFL
RSV
RSV
SAH
Name
MCFC23 - 16
MCFC15 - 8
Name
Name
Reserved.
Input Frequency. These two bits identify the Secondary Reference Clock frequency.
- 00 = 19.44 MHz
- 01 = 8 kHz
- 10 = 1.544 MHz
- 11 = 2.048 MHz
Reserved.
Secondary Acquisition PLL Holdover. This bit goes high whenever the Acquisition PLL
enters Holdover mode. Holdover mode is entered when reference frequency is:
- lost completely
- drifts more than ±30 000 ppm off the nominal frequency
- a large phase hit occurs on the reference clock.
Secondary Acquisition PLL Frequency Limit. This bit goes high whenever the Acquisition
PLL exceeds its capture range of ±104 ppm. This bit can flicker high in the event of a large
excursion of still tolerable input jitter.
Table 18 - Master Clock Frequency Calibration Register 4 (R/W)
Table 19 - Master Clock Frequency Calibration Register 3 (R/W)
Table 20 - Master Clock Frequency Calibration Register 2 (R/W)
Master Clock Frequency Calibration. This most significant byte contains the
31st to 24th bit of the Master Clock Frequency Calibration Register. See
Applications section 4.2 for a detailed description of how to calculate the MCFC
value.
Table 17 - Secondary Acquisition PLL Status Register (R)
Master Clock Frequency Calibration. This byte contains the 23rd
to 16th bit of the Master Clock Frequency Calibration Register.
Master Clock Frequency Calibration. This byte contains the 15th
to 8th bit of the Master Clock Frequency Calibration Register.
Zarlink Semiconductor Inc.
ZL30402
Functional Description
Functional Description
Functional Description
Functional Description
24
Data Sheet
Default
Default
00000
00000
Default
00000
000
000
000