ZL50062 ZARLINK [Zarlink Semiconductor Inc], ZL50062 Datasheet - Page 26

• Manufacturer Part Number: ZL50062
• Description: 16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

4.0
The input pins, LORS and BORS, select whether the Local (LSTo0-31) and Backplane (BSTo0-31) output streams,
respectively, are set to high impedance at the output of the device itself, or are always driven (active HIGH or active
LOW).
Setting LORS/BORS to a LOW state will configure the output streams, LSTo0-31/BSTo0-31, to transmit bi-state
channel data.
Setting LORS/BORS to a HIGH state will configure the output streams, LSTo0-31/BSTo0-31, of the device to
invoke a high impedance output on a per-channel basis. The Local/Backplane Output Enable Bit (LE/BE) of the
Local/Backplane Connection Memory has direct per-channel control on the high impedance state of the
Local/Backplane output streams, L/BSTo0-31. Programming a LOW state in the connection memory LE/BE bit will
set the stream output of the device to high impedance for the duration of the channel period. See “Local Connection
Memory Bit Definition,” on page 34 and “Backplane Connection Memory Bit Definition,” on page 35 for
programming details.
The state of the LORS/BORS pin is detected and the device configured accordingly during a RESET operation,
e.g. following power-up. The LORS/BORS pin is an asynchronous input and is expected to be hard-wired for a
particular system application, although it may be driven under logic control if preferred.
The Local/Backplane output enable control in order of highest priority is: RESET, ODE, OSB, LE/BE.
Bit Advancement = -2
Bit Advancement = -4
Bit Advancement = -6
Bit Advancement = 0
Figure 11 - Local and Backplane Output Advancement Timing Diagram for Data Rate of 16Mbps
Port high impedance Control
BSTo/LSTo0-31
BSTo/LSTo0-31
BSTo/LSTo0-31
BSTo/LSTo0-31
System Clock
131.072 MHz
(input pin)
(Default)
RESET
FP8o
0
0
1
1
1
Table 1 - Local and Backplane Output Enable Control Priority
Bit 1
Bit 1
(input pin)
Bit 1
Ch255
ODE
X
X
0
0
1
Bit 1
Ch255
Bit 0
Ch255
Bit 0
Register bit)
Ch255
(Control
Bit 0
OSB
Zarlink Semiconductor Inc.
X
X
X
X
0
ZL50062/4
Bit 0
Bit 7
26
Memory bit)
Connection
Backplane
Bit 7
(Local /
Bit Advancement, 0
LE/BE
Bit Advancement, -2
Bit Advancement, -4
Bit Advancement, -6
Bit 7
X
X
X
X
X
Bit 7
Bit 6
LORS/BORS
(input pin)
Bit 6
Ch0
0
1
0
1
0
Bit 6
Ch0
Bit 6
Ch0
Bit 5
Ch0
LSTo0-31/
BSTo0-31
Bit 5
HIGH
HIGH
HIGH
HI-Z
HI-Z
Bit 5
Data Sheet
Bit 5
Bit 4
Bit 4