ZL50062 ZARLINK [Zarlink Semiconductor Inc], ZL50062 Datasheet - Page 43

• Manufacturer Part Number: ZL50062
• Description: 16K-Channel Digital Switch with High Jitter Tolerance, Single Rate (2, 4, 8, or 16Mbps), and 64 Inputs and 64 Outputs
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

13.3.1
When SMPL_MODE = LOW, these five bits define the amount of input bit delay adjustment that the receiver uses to
sample each input. Input bit delay adjustment can range up to 7
period. The default sampling point is at the
This can be described as: no. of bits delay = LID[4:0] / 4
For example, if LID[4:0] is set to 10011 (19), the input bit delay = 19 *
When SMPL_MODE = HIGH, the binary value of LID[1:0] refers to the input bit sampling point (
refer to the integer bit delay value (0 to 7 bits). This means that bits can be delayed by an integer value of up to 7
and that the sampling point can vary from
Table 16 illustrates the bit delay and sampling point selection.
Local Input Delay Bits 4-0 (LID[4:0])
LID4
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
Table 16 - Local Input Bit Delay and Sampling Point Programming Table
LID3
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
LIDn
LID2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
LID1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
1
/
3
4
/
4
to
Zarlink Semiconductor Inc.
bit location.
4
/
ZL50062/4
LID0
4
in
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
/
4
43
-bit increments.
SMPL_MODE
Input Data
0 (Default)
Bit Delay
= LOW
1 1/4
1 1/2
1 3/4
2 1/4
2 1/2
2 3/4
3 1/4
3 1/2
3 3/4
4 1/4
4 1/2
4 3/4
5 1/4
5 1/2
5 3/4
6 1/4
6 1/2
6 3/4
1/4
1/2
3/4
1
2
3
4
5
6
3
/
4
1
bit periods forward, with resolution of
/
4
= 4
3
Input Data
0 (Default)
Bit Delay
/
4
.
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
5
5
5
5
6
6
6
6
SMPL_MODE
= HIGH
Input Data
Sampling
Point
1
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
3/4
4/4
1/4
2/4
/
4
to
Data Sheet
4
/
4
). LID[4:2]
1
/
4
bit