ZL50073GAC ZARLINK [Zarlink Semiconductor Inc], ZL50073GAC Datasheet
ZL50073GAC
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ZL50073GAC Summary of contents
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... Copyright 2004-2005, Zarlink Semiconductor Inc. All Rights Reserved Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16 Mbps), and 128 Inputs and 128 Outputs ZL50073GAC • Per-channel constant or variable throughput delay for frame integrity and low latency applications • ...
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Applications • Large Switching Platforms • Central Office Switches • Wireless Base Stations • Multi-service Access Platforms • Media Gateways Description The ZL50073 is a non-blocking Time Division Multiplex (TDM) switch with maximum 32,768 x 32,768 channels. The device can ...
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Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block Init Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Figure 1 - ZL50073 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Table 1 - Data Rate and Maximum Switch Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Change Summary The following table captures the changes from the July 2004 issue. Page Item 12 "Pin Description" - CKo0-3 13 "Pin Description" - DTA, WAIT 53 “AC Electrical Characteristics and CKi0-2 Timing“ 55 Figure 13 "Frame Skew Timing Diagram" ...
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Pin Diagram - ZL50073 484 Ball PBGA (as viewed through top of package) A1 corner identified by metallized marking CKo STiA D[30] D[25] D[20] D[16] D[15] D[11] A [0] ...
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Pin Description Pin F7, F10, F13, F17, G9, G12, V G15, H6, H10, H13, H16, J7, K8, K15, K17, L6, L16, M7, N8, N15, P6, P16, P17, R7, R10, R13, T9, T12, T15, U10, U13, U17 F9, F12, F15, G6, ...
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Pin Description (continued) Pin D6, F5, E3, D1, J3, L5, M3, STiC0-31 M4, U1, U3, AA1, AA2, V7, W8, AB6, V10, AB11, Y14, AB18, U16, AB21, W20, U20, P19, R22, N22, L18, H21, G20, F20, D20, E16 C4, B2, D2, ...
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Pin Description (continued) Pin D4, F4, G3, G2, G1, L2, N3, SToD0-31 T1, U2, T6, V5, AA3, W7, AA7, W10, Y11, Y12, AB17, AA18, W18, V19, AA22, U21, N17, P22, L21, L17, H20, D22, E20, C20, D16 W12 AA13 J2, ...
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Pin Description (continued) Pin A1, AB4, R18, E14 G5, Y6, T19, C17 W15, V14 CK_SEL0-1 L1 A18, J21, M22, R3, V13, W13, Y13, AA16, AA17 AB13, AB14 A11, C11, E11, B11, A10, B10, C10, A9, D10, B9, F11, A8, C9, ...
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Pin Description (continued) Pin C16 D14 C15 A19 B17 D15 B18, E15 C5 ZL50073 Name CS Chip Select Input (5 V Tolerant Input) Active low input used with DS to enable read and write access to the ZL50073. DS Data ...
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Pin Description (continued) Pin B7 A20 D18 B21 A22 C19 E17 1.0 Functional Description 1.1 Overview The device has 128 ST-BUS/GCI-Bus inputs (STiA0 - 31, STiB0 - 31, STiC0 - 31, STiD0 - 31) and 128 ST-BUS/GCI-Bus outputs (SToA0 - ...
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The ZL50073 uses the ST-BUS/GCI-Bus master input frame pulse (FPi0) and the ST-BUS/GCI-Bus master input clock (CKi0) to define the input frame boundary and timing for sampling the ST-BUS/GCI-Bus input streams with various data rates (8.192 Mbps, 16.384 Mbps, 32.768 ...
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Stream Provisioning The ZL50073 is a large switch with a comprehensive list of user configurable, ’per-group’ programmable features. In order to facilitate ease of use, the ZL50073 offers a simple programming model. Streams are grouped in sets of four, ...
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For example: • if input stream group #1 is programmed for 65 Mbps: STiA1 is active; STiB1, STiC1, STiD1 are not active • if output stream group #15 is programmed for 32 Mbps: SToA15 and SToB15 are active; SToC15 and ...
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STiA0 - Mbps STiB0 - 23 Not Active Input Groups Mbps STiC0 - 23 Not Active STiD0 - 23 Not Active STiA24 - Mbps STiB24 - ...
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These additional input clocks and frame pulses can be used as alternative clock sources for the input streams, output streams, and output clocks / frame pulses. The input streams’ clock sources are controlled by the ISSRC1-0 (bits ...
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Nominal Channel n Boundary STi[ 00000 (Default) 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 Example: With a setting of 01111 the sampling point for bit 7 will be 3 ...
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Nominal 8 MHz Clock Nominal 16 MHz Clock Nominal 32/65 MHz Clock Nominal Output Bit Timing OSBA = 00 Level 1 Advance OSBA = 01 Level 2 Advance OSBA = 10 Level 3 Advance OSBA = 11 This programming feature ...
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Lowest data bytes (bits four consecutive message mode channels can be set with one Connection Memory LSB access. Refer to Section 14.1.2, Connection Memory LSB, for programming details. 6.1 Data Memory Read All TDM input ...
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N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 N-2 N-1 CH0 CH1 CH2 CH3 Figure 7 - Data Throughput Delay for Constant Delay 7.2 Variable Delay Mode Variable delay mode ...
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Per-Channel A-Law/µ-Law Translation The ZL50073 provides per channel code translation to be used to adapt pulse code modulation (PCM) voice or data traffic between networks which use different encoding laws. Code translation is available in both Connection Modes and ...
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Frame m Each PRBS detector can be configured to monitor for bit errors in one or more timeslots. The selection of timeslots is configured by the Input BER Enable Control Memory (IBERECM). See Section 14.3.1 for programming ...
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Address (Hex) Table 5 - Example of Address and Byte Significance 10.2 32 bit Bus Operation In 32 bit mode (D16B = 0), all 32 bits of the Data Bus, D31 - 0, may be used for write and read ...
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Bit Bus Operation In 16 bit mode (D16B = 1), D15 - 0 are used for data transfers to/from the ZL50073. D31 - 16 are unused and must be connected to a defined logic level. D15 on the ...
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Address Register (Hex) Description 40200 or Group Control Register (Group 0) 40201 40282 or Input Clock Control Register 40283 40286 or Output Clock Control Register 40287 40284 or Output Clock Control Register 40285 Table Bit Mode Example ...
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Address A, SIZ1 - 0 CS R/W DS Hi-Z Data Hi-Z DTA BERR WAIT The cycle termination signals WAIT & DTA are provided for all bus configurations. 10.4.2 Write Cycle The operation of the write cycle is illustrated in Figure ...
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Address SIZ1 - 0 CS R/W DS Data DTA Hi-Z BERR WAIT The cycle termination signals WAIT & DTA are provided for all bus configurations. 11.0 Power-up and Initialization of the ZL50073 11.1 Device Reset and Initialization The PWR pin ...
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Note: After the PWR reset is removed, and on the application of a suitable master clock input, it takes approximately 1 ms for the internal initialization to complete. • Automatic block initialization of the Connection Memory to all zeros occurs, ...
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Test Reset (TRST) - Resets the JTAG scan structure. This pin is internally pulled to V driven from an external source. When JTAG is not in use, this pin must be tied low for normal operation. The TAP signals ...
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Address (Hex) 40288 - 4028B Block Init Register 4028C - 4028F Block Init Enable 40290- 7FFFF Invalid Address. Access causes Bus error (BERR) 14.0 Detailed Memory and Register Descriptions This section describes all the memories and registers that are used ...
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The mapping of each output stream, SToAn, SToBn, SToCn and SToDn, depends on the programmed bit rate. The address offset range for each stream is illustrated in Table 14. Output Group Data Rate Timeslot Range 65 Mbps 32 Mbps 16 ...
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SToAn 256 257 - 510 511 512 513 - 1021 1022 1023 Table 15 - Connection Memory Timeslot Address Offset Range (continued) 14.1.1 Connection Memory Bit Functions The bit functions of the connection memory are illustrated in Table 16. External ...
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External Read/Write Address: 000000 H Reset Value: 0000 PCF PCF PCF ICL V Bit Name 28 ...
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External Read/Write Address: 000000 H Reset Value: 0000 PCF PCF PCF ICL V Bit Name 9 ...
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Start Output Address Range Address Group (Hex) (Hex) 6 021800 021800 - 021BFF 7 021C00 021C00 - 021FFF 8 022000 022000 - 0223FF 9 022400 022400 - 0227FF 10 022800 022800 - 022BFF 11 022C00 022C00 - 022FFF 12 023000 ...
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Output Group Data Rate Timeslot Range 65 Mbps 32 Mbps 16 Mbps 8 Mbps Table 18 - Connection Memory LSB Stream Address Offset at Various Output Rates Within each stream group, the mapping of each of the actual output streams, ...
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Data Memory The data memory field is a read only address range used to monitor the data being received by the input streams. Addressing into each of the streams is illustrated in Table 19. Start Input Address Group (Hex) ...
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Input Group Data Rate Time-slot Range 8 Mbps Table 20 - Data Memory Stream Address Offset at Various Output Rates (continued) The address ranges for the data memory portion corresponding to each of the actual input streams, STiAn, STiBn, STiCn ...
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Each byte location of the BER Enable Memory contains one read/write BER counter enable (BCE) bit, mapped into the D0 location. If the BCE bit is set, then the BER counter for the corresponding stream and timeslot is enabled for ...
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BER Input Group 31 Table 23 - BER Counter Group and Stream Address Mapping (continued) 14.4 Group Control Registers The ZL50073 addresses the issues of a simple programming model and automatic stream configuration by defining a basic switching bit rate ...
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External Read/Write Address: 40200 - 4027F H Reset Value: 000C000C Bit Name ...
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External Read/Write Address: 40200 - 4027F H Reset Value: 000C000C Bit Name ...
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Input Clock Control Register The Input Clock Control Register is used to select the logic sense of the input clock. External Read/Write Address: 40280 H Reset Value: 0DB ...
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Output Clock Control Register The Output Clock Control Register is used to select the desired source, frequency, and logic sense of the output clocks. The bit functions of the Output Clock Control Register are illustrated in Table 27. External ...
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External Read/Write Address: 40284 H Reset Value: 060D1C3C GCO SEL3 CKO2 CKO2 GCO FPO CKO SRC1 SRC0 SEL1 POL1 POL1 Bit Name 20 GCO GCI-Bus ...
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External Read/Write Address: 40284 H Reset Value: 060D1C3C GCO SEL3 CKO2 CKO2 GCO FPO CKO SRC1 SRC0 SEL1 POL1 POL1 Bit Name 12 FPO Frame ...
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External Read/Write Address: 40284 H Reset Value: 060D1C3C GCO SEL3 CKO2 CKO2 GCO FPO CKO SRC1 SRC0 SEL1 POL1 POL1 RATE1 Bit Name 4 CKO ...
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Block Init Register The Block Init Register bit read/write register at address 040288 - 04028B The Block Init Register is used during block initialization of the connection memory. A block initialization automatically occurs at power-up. However, ...
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DC/AC Electrical Characteristics 1 Absolute Maximum Ratings - Voltages are with respect to ground (V Characteristics 1 Chip I/O Supply Voltage 2 Chip Core Supply Voltage 3 Input Voltage (non-5 V tolerant inputs) 4 Input Voltage (5 V tolerant ...
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DC Electrical Characteristics - Voltages are with respect to ground (VSS) unless otherwise stated. Characteristics 10 Pull-down Current 11 Input Pin Capacitance 12 Output High Voltage 13 Output Low Voltage Note 1: Typical figures are at 25°C, V DD_CORE subject ...
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AC Electrical Characteristics - FPi0-2 and CKi0-2 Timing No. Characteristic (Figure 12) 5 CKi Input Clock High Time 6 CKi Input Clock Low Time 7 CKi Input Clock Rise/Fall Time 8 CKi Input Clock Cycle to Cycle Variation Note ...
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AC Electrical Characteristics - FPi and CKi Skew No. Characteristic (Figure 13) 1 CKi0 to CKi1, 2 Skew Note 1: Characteristics are over recommended operating conditions unless otherwise stated. Note 2: Typical figures are at 25°C, V DD_CORE subject ...
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AC Electrical Characteristics - FPO0-3 and CKO0-3 (65.536 MHz) Timing No. Characteristic 1 FPO0-3 Output Frame Pulse Setup Time 2 FPO0-3 Output Frame Pulse Hold Time 3 CKO0-3 Output Clock Period 1 AC Electrical Characteristics - FPO0-3 and CKO0-3 ...
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FPo0-3 t FPOS CKo0-3 Output Frame Boundary Figure 14 - ST-Bus Frame Pulse and Clock Output Timing FPo0-3 t FPOS CKo0-3 Output Frame Boundary Figure 15 - GCI Frame Pulse and Clock Output Timing AC Electrical Characteristics - Output Clock ...
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AC Electrical Characteristics - Serial Data Timing No. Characteristic (Figure ) 1 CKi to CKo Positive edge Propagation Delay 2 CKi to CKo Negative edge Propagation Delay 3 STi to posedge CKi setup 4 STi to posedge CKi hold ...
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FPi (negative sense) CKo (negative sense) CKi (negative sense) STin STon STon ODE FPi (negative sense) CKo (positive sense) CKi (positive sense) STin STon STon Note 1: CKi frequency is assumed to be twice of the STin data rate, so ...
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AC Electrical Characteristics - Serial Data Timing No. Characteristic (Figure 17) 1 STi to posedge CKo setup 2 STi to posedge CKo hold 3 STi to negedge CKo setup 4 STi to negedge CKo hold 5 Posedge CKo to Output ...
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FPo (negative sense) CKo (negative sense) STin STon STon FPo (negative sense) CKo (positive sense) STin STon STon Note 1: CKo frequency is assumed to be twice of the STin data rate, so that the sampling point is at the ...
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AC Electrical Characteristics - CKo to Other CKo Skew No. Characteristic (Figure 17) 1 CKo1 to CKo0 skew 2 CKo2 to CKo0 skew 3 CKo1 to CKo3 skew 4 CKo2 to CKo3 skew 5 CKo3 to CKo0 skew 6 CKo2 ...
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AC Electrical Characteristics - Microprocessor Bus Interface No Characteristics (Figure , & Figure 20 Recovery 2 CS Recovery 3 CS asserted setup to DS asserted 4 Address, SIZ1-0, R/W setup to DS asserted 5 CS hold from DS ...
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DS (UDS,LDS) t CSRE CS A18-A0 RWN,SIZ D31-D0 READ D31-D0 WRITE Hi-Z DTA BERR Hi-Z WAIT Figure 19 - Microprocessor Bus Interface Timing DS (BE or 1-0 UDS, LDS) ZL50073 t CSS t ADS VALID VALID READ DATA t WDS ...
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AC Electrical Characteristics - IEEE 1149.1 Test Port and PWR Pin Timing No. Characteristic (Figure 21) 1 TCK Clock Period 2 TCK Clock Frequency 3 TCK Clock Pulse Width High 4 TCK Clock Pulse Width Low 5 TMS Set-up ...
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