ZL50073GAC ZARLINK [Zarlink Semiconductor Inc], ZL50073GAC Datasheet - Page 25

• Manufacturer Part Number: ZL50073GAC
• Description: 32 K Channel Digital Switch with High Jitter Tolerance, Rate Conversion per Group of 4 Streams (8, 16, 32 or 64 Mbps)
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Each PRBS detector can be configured to monitor for bit errors in one or more timeslots. The selection of timeslots
is configured by the Input BER Enable Control Memory (IBERECM). See Section 14.3.1 for programming details.
Each detector has an associated 16 bit error counter accessible via the microprocessor interface, as described in
Section 14.3.2, BER Counters. The value of the counter represents the total number of errors detected on the
corresponding input stream. Bit errors are accumulated until the counter is either reset (by writing to the counter or
by resetting the device), or the counter reaches its maximum value, 65,535 (decimal). If more than 65,535 errors
are detected, the counter will hold at the maximum value until reset.
Any number of timeslots may be configured for bit error rate testing; however the user must ensure the following for
correct operation of the BER test function:
1. The number of timeslots enabled for PRBS detection on the input stream must equal the number of timeslots
2. The arrival order of timeslots at the PRBS detector must be the same as the order in which timeslots were trans-
10.0
The ZL50073 has a generic microprocessor port that provides access to the internal Data Memory (read access
only), Connection Memory, and Control Registers.
The port size can be configured to be either 32 bit or 16 bit, controlled by the D16B pin.
The port works with either Motorola or Intel type microprocessor buses, selected by the IM pin.
10.1
The Data Memory, Connection Memory and Control Registers are assigned 32 bit fields in the ZL50073 memory
space. The Address Bus, A18 - 0, controls access to each 32 bit location. Byte addressing is also provided to give
the user programming flexibility, if access to less than 32 bits is required.
Each 32 bit memory or register location spans 4 consecutive addresses. Example:
•
The Least Significant address identifies the Most Significant Byte (MSB) in the 32 bit field, as illustrated in Table 5.
enabled for PRBS generation on the source output stream.
mitted by the PRBS generator. For example, in Figure 9 above, the timeslot order a,b,c must be maintained
through the external path from source TDM output stream to destination TDM input stream.
The 32 bit Group Control Register for TDM Group 0 is located at address range 40200 - 40203 Hex
Addressing
Microprocessor Port
..010111001101101111001010110110001011111011010011100001101...
a
Frame m
b
Figure 9 - Example PRBS Timeslot Insertion
c
Zarlink Semiconductor Inc.
ZL50073
25
Example segment of serial bit pattern
from Stream N PRBS Generator
a
Frame m+1
b
c
Stream N with Channels
for PRBS insertion
a, b and c enabled
Data Sheet