ZL50115 ZARLINK [Zarlink Semiconductor Inc], ZL50115 Datasheet - Page 37

• Manufacturer Part Number: ZL50115
• Description: 32, 64 and 128 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

CPU_TA
CPU_DREQ0
CPU_DREQ1
CPU_IREQO
CPU_IREQ1
Signal
Table 10 - CPU Interface Package Ball Definition (continued)
I/O
OT
OT
OT
O
O
B22
K22
C22
J22
G20
ZL50115/16/17/18/19/20
Package Balls
Zarlink Semiconductor Inc.
37
CPU Transfer Acknowledge. Driven from
tri-state condition on the negative clock
edge of CPU_CLK following the
assertion of CPU_CS. Active low,
asserted from the rising edge of
CPU_CLK. For a read, asserted when
valid data is available at CPU_DATA.
The data is then read by the host on the
following rising edge of CPU_CLK. For a
write, is asserted when the ZL5011x is
ready to accept data from the host. The
data is written on the rising edge of
CPU_CLK following the assertion.
Returns to tri-state from the negative
clock edge of CPU_CLK following the
de-assertion of CPU_CS.
CPU DMA 0 Request Output Active low
synchronous to CPU_CLK rising edge.
Asserted by ZL5011x to request the host
initiates a DMA write. Only used for DMA
transfers, not for normal register access.
CPU DMA 1 Request
Active low synchronous to CPU_CLK
rising edge. Asserted by ZL5011x to
indicate packet data is ready for
transmission to the CPU, and request
the host initiates a DMA read. Only used
for DMA transfers, not for normal
register access.
CPU Interrupt 0 Request (Active Low)
CPU Interrupt 1 Request (Active Low)
Description
Data Sheet