ZL50115 ZARLINK [Zarlink Semiconductor Inc], ZL50115 Datasheet - Page 50

• Manufacturer Part Number: ZL50115
• Description: 32, 64 and 128 Channel CESoP Processors
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

6.3.2
The ZL5011x is programmable such that the frame/clock polarity and clock alignment can be set to any desired
combination. Table 21 shows a brief summary of four different TDM formats; ST-BUS, H.110, H-MVIP, and Generic
(synchronous mode only), for more information see the relevant specifications shown. There are many additional
formats for TDM transmission not depicted in Table 21, but the flexibility of the port will cover almost any scenario.
The overall data format is set for the entire TDM Interface device, rather than on a per stream basis. It is possible to
control the polarity of the master clock and frame pulse outputs, independent of the chosen data format (used when
operating in synchronous master mode).
H-MVIP
Generic
Format
ST-bus
H.110
Data
Table 21 - Some of the TDM Port Formats Accepted by the ZL50115/16/17/18/19/20 Family
Structured TDM Port Data Formats
(Mbps)
2.048
8.192
2.048
8.192
2.048
2.048
8.192
2.048
8.192
Data
Rate
channels
Number
frame
128
128
128
128
per
32
32
32
32
32
of
ZL50115/16/17/18/19/20
16.384
16.384
Clock
(MHz)
2.048
4.096
8.192
2.048
4.096
2.048
8.192
Freq.
Zarlink Semiconductor Inc.
Nominal
Frame
Width
Pulse
(ns)
244
244
122
244
244
244
488
122
61
50
Negative
Negative
Negative
Negative
Negative
Negative
Negative
Polarity
Positive
Positive
Frame
Pulse
Falling
Falling
Falling
Falling
Rising
Rising
Rising
Rising
Rising
clock
Frame Boundary
Edge
Edge
Edge
Edge
Edge
Edge
Edge
Edge
edge
Alignment
Straddles
boundary
Straddles
boundary
Straddles
boundary
Straddles
boundary
Straddles
boundary
Straddles
boundary
Straddles
boundary
edge of
edge of
Rising
Rising
frame
pulse
clock
clock
Data Sheet
MSAN-126
Standard
(Issue 4)
Release
H-MVIP
Zarlink
Rev B
ECTF
H.110
1.1a