ZL50232GDC ZARLINK [Zarlink Semiconductor Inc], ZL50232GDC Datasheet
ZL50232GDC
Related parts for ZL50232GDC
ZL50232GDC Summary of contents
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Features • Independent multiple channels of echo cancellation; from 32 channels channels of 128 ms with the ability to mix channels at 128 any combination • Independent Power Down mode ...
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Description The ZL50232 Voice Echo Canceller implements a cost effective solution for telephony voice-band echo cancellation conforming to ITU-T G.168 requirements. The ZL50232 architecture contains 16 groups of two echo cancellers (ECA and ECB) which can be configured to provide ...
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A V IC0 V V c4i SS SS DD1 B V IC0 V IC0 DD1 F0i SS C IC0 IC0 DD1 SS D IC0 ...
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Pin Description Pin # Pin Name 208-Ball LBGA V A1, A3,A7,A11, A13, SS A15, A16, B2, B6, B8, B12, B14, B15, B16, C3, C5, C7, C9, C11, C12, C13, C14, C16, D4, D8, D10, D12, D13, E3, E4, E14, F13, ...
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Pin Description (continued) Pin # Pin Name 208-Ball LBGA R11 DS R13 CS R5 R/W R7 DTA D0..D7 T2,T4,T6,T8,T9,T11, T13,T15 A0..A10 P16,N16,M16,L16,K16, J16,H16,G16,F16,E16, D16 ODE B13 Sout A8 Rout B9 Sin B11 Rin B7 B5 F0i A4 C4i MCLK G2 ...
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Pin Description (continued) Pin # Pin Name 208-Ball LBGA Fsel H2 PLLVss1 K3 PLLVss2 PLLV K4 DD TMS M2 TDI M1 TDO N1 TCK P1 N2 TRST RESET R3 1.0 Device Overview The ZL50232 architecture contains 32 echo cancellers divided ...
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Each echo canceller contains the following main elements (see Figure 4). • Adaptive Filter for estimating the echo channel • Subtractor for cancelling the echo • Double-Talk detector for disabling the filter adaptation during periods of double-talk • Path Change ...
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Double-Talk Detector Double-Talk is defined as those periods of time when signal energy is present in both directions simultaneously. When this happens necessary to disable the filter adaptation to prevent divergence of the Adaptive Filter coefficients. Note ...
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Non-Linear Processor (NLP) After echo cancellation, there is always a small amount of residual echo which may still be audible. The ZL50232 uses Zarlink’s patented Advanced NLP to remove residual echo signals which have a level lower than the ...
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The Advanced NLP uses a new noise ramping scheme to quickly and more accurately estimate the background noise level. The noise ramping method of the original NLP can also be used. The InjCtrl bit in Control Register 3 selects the ...
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In response to a valid disable tone, the echo canceller must be switched from the Enable Adaptation state to the Bypass state. This can be done in two ways, automatically or externally. In automatic mode, the Tone Detectors internally control ...
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Device Configuration The ZL50232 architecture contains 32 echo cancellers divided into 16 groups. Each group has two echo cancellers which can be individually controlled (Echo Canceller A (ECA) and Echo Canceller B (ECB)). They can be set in three ...
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Back-to-Back configuration is selected by writing a “1” into the BBM bit of Control Register 1 for both Echo Canceller A and Echo Canceller B for a given group of echo canceller. Table 4 shows the 16 groups of 2 ...
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In Back-to-Back configuration, writing a “1” into the MuteR bit of Echo Canceller A, Control Register 2, causes quiet code to be transmitted on Rout. Writing a “1” into the MuteS bit of Echo Canceller A, Control Register 2, causes ...
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F0i ST-BUS F0i GCI interface Rin/Sin Channel 0 Rout/Sout Note: Refer to Figure 12 and Figure 13 for timing details. Figure 9 - ST-BUS and GCI Interface Channel Assignment for 2 Mbps Data Streams Base Echo Canceller A Address + ...
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Memory Mapped Control and Status Registers Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual ported memory is mapped into segments on a “per channel” basis to monitor and control ...
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Back-to-Back Configuration For a given group (group 0 to 15), only one PCM I/O channel is active (Echo Canceller A) and the other channel carries quiet code. For example, group 5, Echo Canceller A (Channel 10) will be active ...
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Figure 11 - Power Up Sequence Flow Diagram 6.5 Power Management Each group of echo cancellers can be placed in Power Down mode by writing a “0” into the PWUP bit in their respective Main Control Register. When a given ...
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Interrupts The ZL50232 provides an interrupt pin (IRQ) to indicate to the HOST processor when a G.164 or G.165 Tone Disable is detected and released. Although the ZL50232 may be configured to react automatically to tone disable status on ...
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Test Reset (TRST) This pin is used to reset the JTAG scan structure. This pin is internally pulled to V 7.2 Instruction Register In accordance with the IEEE 1149.1 standard, the ZL50232 uses public instructions. The JTAG Interface contains ...
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DC Electrical Characteristics - Voltages are with respect to ground (V Characteristics Static Supply Current 1 IDD_IO (V = 3.3 V) DD1 IDD_CORE (V = 1.8 V) DD2 2 Power Consumption Input High Voltage P U ...
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AC Electrical Characteristics - Frame Pulse and C4i Characteristic 1 Frame pulse width (ST-BUS, GCI) 2 Frame Pulse Setup time before C4i falling (ST-BUS or GCI) 3 Frame Pulse Hold Time from C4i falling (ST-BUS or GCI) 4 C4i ...
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AC Electrical Characteristics - Motorola Non-Multiplexed Bus Mode Characteristics 1 CS setup from DS falling 2 R/W setup from DS falling 3 Address setup from DS falling 4 CS hold after DS rising 5 R/W hold after DS rising ...
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FPW F0i t t FPS FPH C4i t SOD Sout/Rout Bit 7, Channel 31 Bit 0, Channel 0 t SIS Sin/Rin Bit 7, Channel 31 Bit 0, Channel 0 Figure 13 - GCI Interface Timing at 2.048 Mbps ODE ...
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DS CS R/W A0-A10 D0-D7 READ D0-D7 WRITE DTA IRQ Figure 16 - Motorola Non-Multiplexed Bus Timing ZL50232 t CSS t RWS t ADS VALID ADDRESS t DDR VALID READ DATA t DSW VALID WRITE DATA t AKD t IRD ...
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Register Description Echo Canceller A (ECA): Control Register 1 Power-up 00 Bit 7 Bit 6 Reset INJDis Reset When high, the power-up initialization is executed. This presets all register bits including this bit and clears the Adaptive Filter coefficients. ...
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Power-up 00 hex Bit 7 Bit 6 TDis PHDis NLPDis TDis When high, tone detection is disabled. When low, tone detection is enabled. When both Echo Cancellers A and B TDis bits are high, Tone Disable processors are disabled entirely ...
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Power-up 00 hex Bit 7 Bit 6 Bit 5 Reserve TD DTDet Functional Description of Register Bits Reserve Reserved bit TD Logic high indicates the presence of a 2100Hz tone DTDet Logic high indicates the presence of a double-talk condition ...
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Amplitude of MU 1.0 Flat Delay (FD ) 7-0 -16 2 Functional Description of Register Bits The Exponential Decay registers (Decay Step Number and Decay Step Size) and Flat Delay register allow the LMS adaptation step-size (MU programmed ...
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Power-up FB hex Bit 7 Bit 6 Bit 5 NLRun2 InjCtrl NLRun1 NLRun2 When high, the comfort noise level estimator actively rejects double-talk as being background noise. When low, the noise level estimator makes no such distinction. InjCtrl Selects which ...
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Power-up 54 hex Bit 7 Bit 6 Bit 5 0 SD2 SD1 Functional Description of Register Bits 0 Must be set to zero. SupDec These three bits (SD2,SD1,SD0) control how long the echo canceller remains in a fast convergence state ...
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ECA: Rin Peak Detect Register 2 (RP) Power-up N/A ECB: Rin Peak Detect Register 2 (RP) Bit 7 Bit 6 Bit 5 RP15 RP14 RP13 Power-up ECA: Rin Peak Detect Register 1 (RP) N/A ECB: Rin Peak Detect Register 1 ...
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ECA: Error Peak Detect Register 2 (EP) Power-up N/A ECB: Error Peak Detect Register 2 (EP) Bit 7 Bit 6 Bit 5 EP15 EP14 EP13 ECA: Error Peak Detect Register 1 (EP) Power-up N/A ECB: Error Peak Detect Register 1 ...
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ECA: Non-Linear Processor Threshold Register 2 Power-up 0C ECB: Non-Linear Processor Threshold Register 2 hex Bit 7 Bit 6 Bit 5 NLP15 NLP14 NLP13 ECA: Non-Linear Processor Threshold Register 1 Power-up E0 ECB: Non-Linear Processor Threshold Register 1 hex Bit ...
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Power-up 44 hex Bit 7 Bit 6 Bit 5 0 Rin2 Rin1 Power-up 44 hex Bit 7 Bit 6 Bit 5 0 Sin2 Sin1 Functional Description of Register Bits This register is used to select gain values on RIN, ROUT, ...
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Main Control Register 0 (EC Group 0) Power-up 00 hex Bit 7 Bit 6 Bit 5 WR_all ODE MIRQ Functional Description of Register Bits Write all control bit: When high, Group 0-15 Echo Cancellers Registers are mapped into 0000 WR_all ...
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Main Control Register 1 (EC Group 1) Main Control Register 2 (EC Group 2) Main Control Register 3 (EC Group 3) Main Control Register 4 (EC Group 4) Main Control Register 5 (EC Group 5) Main Control Register 6 (EC ...
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Power-up 00 hex Bit 7 Bit 6 Bit 5 IRQ 0 0 Functional Description of Register Bits IRQ Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register is read. Logic Low indicates that ...
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