ZL50232GDC ZARLINK [Zarlink Semiconductor Inc], ZL50232GDC Datasheet - Page 38

• Manufacturer Part Number: ZL50232GDC
• Description: 32 Channel Voice Echo Canceller
• Manufacturer: ZARLINK [Zarlink Semiconductor Inc]

Reserve
Reserve
I<4:0>
Bit 7
Bit 7
IRQ
IRQ
Tirq
0
0
Logic high indicates an interrupt has occurred. IRQ bit is cleared after the Interrupt FIFO register
is read. Logic Low indicates that no interrupt is pending and the FIFO is empty.
Unused bit. Always zero.
Unused bit. Always zero.
I<4:0> binary code indicates the channel number at which a Tone Detector state change has
occurred. Note: Whenever a Tone Disable is detected or released, an interrupt is generated.
Reserved bits. Must always be set to zero for normal operation.
Test IRQ: Useful for the application engineer to verify the interrupt service routine. When high,
any change to MTDBI and MTDAI bits of the Main Control Register will cause an interrupt and its
corresponding channel number will be available from the Interrupt FIFO Register. When low,
normal operation is selected.
Reserve
Bit 6
Bit 6
Power-up 00
0
Power-up 00
Reserve
Bit 5
Bit 5
hex
hex
0
Functional Description of Register Bits
Functional Description of Register Bits
Interrupt FIFO Register
Reserve
Zarlink Semiconductor Inc.
Bit 4
Bit 4
I4
Test Register
ZL50232
38
Reserve
Bit 3
Bit 3
I3
Reserve
R/W Address: 410
R/W Address: 411
Bit 2
Bit 2
I2
Reserve
Bit 1
Bit 1
I1
hex
hex
Data Sheet
Bit 0
Bit 0
Tirq
I0