ZL50232GDC ZARLINK [Zarlink Semiconductor Inc], ZL50232GDC Datasheet - Page 33
ZL50232GDC
Manufacturer Part Number
ZL50232GDC
Description
32 Channel Voice Echo Canceller
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50232GDC.pdf
(41 pages)
These peak detector registers allow the user to monitor the error signal peak level. The information is in 16 bit
2’s complement linear coded format presented in two 8 bit registers for each echo canceller. The high byte is in
Register 2 and the low byte is in Register 1.
This register allows the user to program the level of Double-Talk Detection Threshold (DTDT). The 16 bit 2’s
complement linear value defaults to 4800
0 dB. The high byte is in Register 2 and the low byte is in Register 1.
DTDT15
DTDT7
Bit 7
Bit 7
EP15
Bit 7
Bit 7
EP7
Power-up
Power-up
Power-up
Power-up
48
00
N/A
N/A
hex
hex
DTDT14
DTDT6
Bit 6
Bit 6
EP14
Bit 6
Bit 6
EP6
DTDT13
DTDT5
ECA: Double-Talk Detection Threshold Register 2
ECB: Double-Talk Detection Threshold Register 2
ECA: Double-Talk Detection Threshold Register 1
ECB: Double-Talk Detection Threshold Register 1
Bit 5
Bit 5
EP13
Bit 5
Bit 5
EP5
ECA: Error Peak Detect Register 2 (EP)
ECB: Error Peak Detect Register 2 (EP)
ECA: Error Peak Detect Register 1 (EP)
ECB: Error Peak Detect Register 1 (EP)
Functional Description of Register Bits
Functional Description of Register Bits
DTDT12
DTDT4
hex
Bit 4
Bit 4
EP12
= 0.5625 or -5 dB. The maximum value is 7FFF
Bit 4
Bit 4
EP4
Zarlink Semiconductor Inc.
ZL50232
33
DTDT11
DTDT3
Bit 3
Bit 3
EP11
Bit 3
Bit 3
EP3
DTDT10
DTDT2
EP10
Bit 2
Bit 2
Bit 2
Bit 2
EP2
11
31
10
30
15
35
14
34
DTDT9
DTDT1
Bit 1
Bit 1
EP9
EP1
Bit 1
Bit 1
hex
hex
hex
hex
hex
hex
hex
hex
Read Address:
Read Address:
Read Address:
Read Address:
R/W Address:
R/W Address:
R/W Address:
R/W Address:
hex
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
= 0.9999 or
Data Sheet
DTDT8
DTDT0
Bit 0
Bit 0
Bit 0
Bit 0
EP8
EP0