ZL50233GDC ZARLINK [Zarlink Semiconductor Inc], ZL50233GDC Datasheet - Page 16
ZL50233GDC
Manufacturer Part Number
ZL50233GDC
Description
4 Channel Voice Echo Cancellor
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50233GDC.pdf
(37 pages)
16
6.0
Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual
ported memory is mapped into segments on a “per channel” basis to monitor and control each individual echo
canceller and associated PCM channels. For example, in Normal configuration, echo canceller #3 makes use of
Echo Canceller B from group 2. It occupies the internal address space from 060
channel #3 on all serial PCM I/O streams.
As illustrated in Table 3, the “per channel” registers provide independent control and status bits for each echo
canceller. Figure 10 shows the memory map of the control/status register blocks for all echo cancellers.
When Extended Delay or Back-to-Back configuration is selected, Control Register 1 of ECA and ECB and Control
Register 2 of the selected group of echo cancellers require special care. Refer to the Register description section.
Table 4 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended
Delay or Back-to-Back.
6.1
For a given group (group 0 to 1), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B,
channels 2 and 3 are active.
6.2
For a given group (group 0 or 1), only one PCM I/O channel is active (Echo Canceller A) and the other channel
carries quiet code. For example, group 0, Echo Canceller A (Channel 0) will be active and Echo Canceller B
(Channel 1) will carry quiet code.
6.3
For a given group (group 0 or 1), only one PCM I/O channel is active (Echo Canceller A) and the other channel
carries quiet code. For example, group 1, Echo Canceller A (Channel 2) will be active and Echo Canceller B
(Channel 3) will carry quiet code.
ZL50233
Normal Configuration
Extended Delay Configuration
Back-to-Back Configuration
Memory Mapped Control and Status registers
Group 0
Echo
Cancellers
Registers
Group 1
Echo
Cancellers
Registers
Table 4 - Group and Channel allocation
Channel 0, ECA Ctrl/Stat Registers
Channel 1, ECB Ctrl/Stat Registers
Channel 2, ECA Ctrl/Stat Registers
Channel 3, ECB Ctrl/Stat Registers
Main Control Registers <7:0>
Interrupt FIFO Register
Test Register
Reserved Test Register
Figure 10 - Memory Mapping
Group
Zarlink Semiconductor Inc.
0
1
Channels
0, 1
2, 3
0000h -->
0020h -->
0040h -->
0060h -->
0400h --> 0407h
0410h
0411h
0412h ---> FFFFh
001Fh
003Fh
005Fh
007Fh
hex
to 07F
hex
and interfaces to PCM
Data Sheet