ZL50235GD ZARLINK [Zarlink Semiconductor Inc], ZL50235GD Datasheet - Page 16
ZL50235GD
Manufacturer Part Number
ZL50235GD
Description
16 Channel Voice Echo Canceller
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50235GD.pdf
(39 pages)
16
6.0
Internal memory and registers are memory mapped into the address space of the HOST interface. The internal dual
ported memory is mapped into segments on a “per channel” basis to monitor and control each individual echo
canceller and associated PCM channels. For example, in Normal configuration, echo canceller #5 makes use of
Echo Canceller B from group 2. It occupies the internal address space from 0A0
PCM channel #5 on all serial PCM I/O streams.
As illustrated in Table 3, the “per channel” registers provide independent control and status bits for each echo
canceller. Figure 10 shows the memory map of the control/status register blocks for all echo cancellers.
When Extended Delay or Back-to-Back configuration is selected, Control Register 1 of ECA and ECB and Control
Register 2 of the selected group of echo cancellers require special care. Refer to the Register description section.
Table 4 is a list of the channels used for the 16 groups of echo cancellers when they are configured as Extended
Delay or Back-to-Back.
6.1
For a given group (group 0 to 7), 2 PCM I/O channels are used. For example, group 1 Echo Cancellers A and B,
channels 2 and 3 are active.
6.2
For a given group (group 0 to 7), only one PCM I/O channel is active (Echo Canceller A) and the other channel
carries quiet code. For example, group 2, Echo Canceller A (Channel 4) will be active and Echo Canceller B
(Channel 5) will carry quiet code.
6.3
For a given group (group 0 to 7), only one PCM I/O channel is active (Echo Canceller A) and the other channel
carries quiet code. For example, group 5, Echo Canceller A (Channel 10) will be active and Echo Canceller B
(Channel 11) will carry quiet code.
ZL50235
Normal Configuration
Extended Delay Configuration
Back-to-Back Configuration
Memory Mapped Control and Status registers
Table 4 - Group and Channel allocation
Group
Zarlink Semiconductor Inc.
0
1
2
3
4
5
6
7
Channels
12, 13
14, 15
10, 11
0, 1
2, 3
4, 5
6, 7
8, 9
hex
to 0BF
hex
and interfaces to
Data Sheet