ZL50235GD ZARLINK [Zarlink Semiconductor Inc], ZL50235GD Datasheet - Page 22
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ZL50235GD
Manufacturer Part Number
ZL50235GD
Description
16 Channel Voice Echo Canceller
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50235GD.pdf
(39 pages)
22
ZL50235
Note: Bits marked with “0” are reserved bits and should be written “0”
Reserve
Reserve
Reserve
Reserve
Reserve
DTDet
TDG
Bit 7
Bit 7
Bit 7
NS7
Bit 7
FD7
NB
TD
0
Power-up
Power-up
Power-up
Power-up
00
00
00
00
hex
hex
hex
hex
Reserved bit.
Logic high indicates the presence of a 2100Hz tone.
Logic high indicates the presence of a double-talk condition.
Reserved bit.
Reserved bit.
Reserved bit.
Tone detection status bit gated with the AutoTD bit. (Control Register 2)
Logic high indicates that AutoTD has been enabled and the tone detector has detected
the presence of a 2100Hz tone.
Logic high indicates the presence of a narrow-band signal on Rin.
Bit 6
Bit 6
Bit 6
Bit 6
FD6
NS6
TD
0
ECA: Decay Step Size Control Register (NS)
ECB: Decay Step Size Control Register (NS)
DTDet
Bit 5
Bit 5
Bit 5
NS5
Bit 5
FD5
Functional Description of Register Bits
0
ECA: Decay Step Size Register (NS)
ECB: Decay Step Size Register (NS)
ECA: Flat Delay Register (FD)
ECB: Flat Delay Register (FD)
ECA: Status Register
ECB: Status Register
Zarlink Semiconductor Inc.
Reserve
Bit 4
Bit 4
Bit 4
NS4
Bit 4
FD4
0
Reserve
Bit 3
Bit 3
Bit 3
NS3
Bit 3
FD3
0
Reserve
SSC2
Bit 2
Bit 2
Bit 2
NS2
Bit 2
FD2
02
22
04
24
07
06
26
27
SSC1
hex
hex
hex
hex
hex
hex
hex
TDG
Bit 1
Bit 1
hex
Bit 1
NS1
Bit 1
FD1
R/W Address:
R/W Address:
R/W Address:
R/W Address:
R/W Address:
R/W Address:
R/W Address:
R/W Address:
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
Data Sheet
SSC0
Bit 0
Bit 0
FD0
Bit 0
NS0
Bit 0
NB