ZL50235GD ZARLINK [Zarlink Semiconductor Inc], ZL50235GD Datasheet - Page 28
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ZL50235GD
Manufacturer Part Number
ZL50235GD
Description
16 Channel Voice Echo Canceller
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50235GD.pdf
(39 pages)
28
ZL50235
This register allows the user to program the level of MU. MU is a 16 bit 2’s complement value which defaults to
4000
is in Register 1.
This register allows the user to program the level of the Non-Linear Processor Threshold (NLPTHR). The 16 bit
2’s complement linear value defaults to 0CE0
dB. The high byte is in Register 2 and the low byte is in Register 1.
NLP15
MU15
NLP7
MU7
Bit 7
Bit 7
Bit 7
Bit 7
hex
Power-up
Power-up
Power-up
Power-up
0C
= 1.0 The maximum value is 7FFF
E0
40
00
hex
hex
hex
hex
NLP14
MU14
NLP6
MU6
Bit 6
Bit 6
Bit 6
Bit 6
ECA: Non-Linear Processor Threshold Register 2
ECB: Non-Linear Processor Threshold Register 2
ECA: Non-Linear Processor Threshold Register 1
ECB: Non-Linear Processor Threshold Register 1
NLP13
NLP5
MU13
Bit 5
Bit 5
MU5
Bit 5
Bit 5
ECA: Adaptation Step Size Register 2 (MU)
ECB: Adaptation Step Size Register 2 (MU)
ECA: Adaptation Step Size Register 1 (MU)
ECB: Adaptation Step Size Register 1 (MU)
Functional Description of Register Bits
Functional Description of Register Bits
NLP12
NLP4
MU12
Bit 4
Bit 4
hex
MU4
Bit 4
Bit 4
hex
Zarlink Semiconductor Inc.
or 1.9999 decimal. The high byte is in Register 2 and the low byte
(NLPTHR)
(NLPTHR)
(NLPTHR)
(NLPTHR)
= 0.1 or -20.0dB. The maximum value is 7FFF
NLP11
NLP3
MU11
Bit 3
Bit 3
MU3
Bit 3
Bit 3
NLP10
NLP2
Bit 2
Bit 2
MU10
MU2
Bit 2
Bit 2
19
39
18
38
1B
3B
1A
3A
NLP9
NLP1
Bit 1
Bit 1
MU9
MU1
Bit 1
Bit 1
hex
hex
hex
hex
hex
hex
hex
hex
R/W Address:
R/W Address:
R/W Address:
R/W Address:
R/W Address:
R/W Address:
R/W Address:
R/W Address:
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
+ Base Address
hex
= 0.9999 or 0
Data Sheet
NLP8
NLP0
Bit 0
Bit 0
MU8
MU0
Bit 0
Bit 0