ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 76

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ZL50400GDC

Manufacturer Part Number
ZL50400GDC
Description
Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
12.3.4.11
CPU Address:h324
Accessed by CPU (RO)
CPU receive queue status
12.3.4.12
CPU Address:h325
Accessed by CPU (RW)
MAC01, MAC23, MAC45, MAC67, and MAC9 registers are used with the MAC0~5 registers to form the CPU MAC
address on a per port basis.
12.3.4.13
CPU Address:h326
Accessed by CPU (RW)
12.3.4.14
CPU Address:h327
Accessed by CPU (RW)
Bits [2:0]:
Bit [3]:
Bits [6:4]:
Bit [7]:
Bits [3:0]:
Bits [7:4]:
Bits [2:0]:
Bit [3]:
Bits [6:4]:
Bit [7]:
Bits [2:0]:
Bit [3]:
Bits [6:4]:
Bit [7]:
RQSS – Receive Queue Status
MAC01 – Increment MAC port 0,1 address
MAC23 – Increment MAC port 2,3 address
MAC45 – Increment MAC port 4,5 address
Bits [42:40] of Port 2 CPU MAC address
Reserved
Bits [42:40] of Port 3 CPU MAC address
Reserved
Bits [42:40] of Port 0 CPU MAC address
Reserved
Bits [42:40] of Port 1 CPU MAC address
Reserved
Unicast Queue 3 to 0 not empty
0: Empty
1: Not Empty
Multicast Queue 3 to 0 not empty
Bits [42:40] of Port 4 CPU MAC address
Reserved
Bits [42:40] of Port 5 CPU MAC address
Reserved
Zarlink Semiconductor Inc.
ZL50400
76
Data Sheet

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