ZL50400GDC ZARLINK [Zarlink Semiconductor Inc], ZL50400GDC Datasheet - Page 77
ZL50400GDC
Manufacturer Part Number
ZL50400GDC
Description
Lightly Managed/Unmanaged 9-Port 10/100 M Ethernet Switch
Manufacturer
ZARLINK [Zarlink Semiconductor Inc]
Datasheet
1.ZL50400GDC.pdf
(124 pages)
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12.3.4.15
CPU Address:h328
Accessed by CPU (RW)
12.3.4.16
CPU Address:h329
Accessed by CPU (RW)
12.3.4.17
CPU Address:h330-336
Accessed by CPU, (R/W)
CPU Queue insertion command
Bits [2:0]:
Bit [3]:
Bits [6:4]:
Bit [7]:
Bits [9:0]:
Bits [13:10]
Bits [20:14]
Bits [35:21]
Bits [50:36]
Bit [51]
Bits [54:52]
Bit [55]
Bits [7:0]:
MAC67 – Increment MAC port 6,7 address
MAC9 – Increment MAC port 9 address
CPUQINS0 - CPUQINS6 – CPU Queue Insertion Command
55
CQ6
Bits [47:40] of Port 9 CPU MAC address
Destination Map (MMAC, CPU, port 7-0).
Priority
Number of granules for the frame
Tail pointer
Header Pointer
Multicast frame (has to be one if more than one destination port)
Reserved
Command valid (will be processed on the rising edge of the signal)
Bits [42:40] of Port 6 CPU MAC address
Reserved
Bits [42:40] of Port 7 CPU MAC address
Reserved
CQ5
CQ4
Zarlink Semiconductor Inc.
ZL50400
CQ3
77
CQ2
CQ1
CQ0
0
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