TFRA84J13DS0 AGERE [Agere Systems], TFRA84J13DS0 Datasheet
TFRA84J13DS0
Related parts for TFRA84J13DS0
TFRA84J13DS0 Summary of contents
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... The Ultramapper™ Family Register Description and the Ultramapper Family System Design Guide. These documents are available on a password protected website. The Ultraframer Product Description (this document) and the Ultraframer Hardware Design Guide. These documents are available on the public website shown below. ...
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... Transmit Direction .................................................................................................................................10 5.1.2 E13 MUX ..........................................................................................................................................................10 5.2 Multirate Cross Connect (MRXC) ..............................................................................................................................11 5.3 DS1 Digital Jitter Attenuator (DS1/E1 DJA) ...............................................................................................................11 5.4 Test Pattern Generator/Monitor (TPG/TPM) .............................................................................................................11 5.5 Clock Generator (CG) ................................................................................................................................................12 5.6 Framer (FRM) ............................................................................................................................................................12 5.6.1 Line Decoder/Encoder .....................................................................................................................................12 5.6.2 Receive Frame Aligner/Transmit Frame Formatter ..........................................................................................12 5.6.3 Receive Performance Monitor ..........................................................................................................................12 5.6.4 Signaling Processor .........................................................................................................................................13 5.6.5 Facility Data Link (FDL) Processor ..................................................................................................................13 5.6.6 HDLC Unit ........................................................................................................................................................13 6 Glossary ...
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... Any sink or receiving channel can be replaced by a test pattern monitor, which can detect and count bit errors or misconfigurations, and/or detect idle conditions or AIS. Datalink (DS1-ESF DL) and SSM (E1 multiframe Sa) fields read/writable. Supports all Ultraframer modes of operation. Complies with T1.107, T1.231, T1.403, G.703, G.704, and O.150 2.2 M13/E13 MUX (x3) 2 ...
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... Multicast operation (one to many) is supported for 168 sources and destinations. Any mix of DS2, E2, DS3 signals can interconnect. Multirate cross connect allows signals to/from E13 modules from/to the framer, TPG/TPM, and external pins. There are signals to/from E13 from/to external pins. ...
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... Loopbacks can be configured to sectionalize a circuit for identifying faults or misconfiguration during out of service maintenance. Fast alarm channels are supported for E13 and M13 to framer interconnects for alarm indication signal (AIS or blue alarm). This feature reduces the propagation delay of the alarms by eliminating multiple integration of alarm conditions. ...
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... Ultraframer device integrates M13/E13 multiplex/demultiplex functions and the primary rate framing function. Each interface consists of a fully integrated, full featured, primary rate framer with HDLC formatter for facility data link access. It also provides alarm reporting and bidirectional performance monitoring. The TFRA84J13 provides glueless inter- connection to analog line interface units and time-slot interchangers ...
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... The DS1s/E1s will be received/transmitted by the device via the LINERX/TXDATA pins. All three instances of the 28/21 channel M13/E13 MUXs are configured identically for M13/E13 mode. All three instances of the 28/21 channel framers are configured identically for the transport mode of operation. DS3 to/from E1 application is also possible. ...
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... The PSB interface consists of a 16-bit wide parallel bus operating at 19.44 Mbits/s. All three instances of the 28/21 channel M13/E13 MUXs are configured identically for M13/E13 mode. All three instances of the 28/21 channel framers are configured identically for switching mode of operation. DS3 to/from E1 to/from E0 application is also possible (x3 DS3 to/from 2016 E0s). ...
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... CHI can be programmed to operate at 8.192 MHz or 16.384 MHz clock and data rates. — The PSB interface consists of a 16-bit wide parallel bus operating at 19.44 Mbits/s. All three instances of the 28/21 channel framers are configured identically for switching mode (DS1/E1 to/from DS0/E0) of operation. ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 5 Block Description 5.1 M13/E13 Multiplexer (M13/E13 MUX) The M13/E13 block (three blocks per device highly configurable multiplexer/demultiplexer for which each block can be configured for M13 or E13 operation. The features are as described below. 5.1.1 M13 MUX The M13 may operate in the C-bit parity or M23 mode mixed M13/M23 mode ...
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... The TPG feeds one or more DS1/E1/DS2 test signals (via data, clock, and FS (DS1/E1 only) or AIS signal paths) to the multirate cross connect, which can redistribute or broadcast these signals to any valid channel in the framer, external I/O, or M13/E13 MUX. Any channel arriving at the multirate cross connect can be routed to the test monitor ...
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... PDH clocks, based upon the logic states on the MODE[2:0]_PLL pins (see the Ultraframer Hardware Design Guide). 5.6 Framer (FRM) The DS1/J1/E1 framer block’s (three per device) internal components are described in the following sections. A par- ticular application will determine which of the components within the framer are used. ...
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... TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 5.6.4 Signaling Processor The signaling processor supports the following modes: Superframe (D4, SLC-96): 2-state, 4-state, and 16-state VT 1.5 SPE: 2-state, 4-state, and 16-state Extended superframe: 2-state, 4-state, and 16-state CEPT: common channel signaling (CCS) (TS-16) Transparent (pass through) signaling ...
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... Agere, Agere Systems, and the Agere logo are registered trademarks of Agere Systems Inc. Ultramapper is a trademark of Agere Systems Inc. Copyright © 2005 Agere Systems Inc. All Rights Reserved April 29, 2005 DS03-076BBAC-4 (Replaces DS03-076BBAC-3) TFRA84J13 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 FEBE Far-end block error HDB3 ...