SMC256BFY6 STMICROELECTRONICS [STMicroelectronics], SMC256BFY6 Datasheet - Page 30

• Manufacturer Part Number: SMC256BFY6
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Command Interface
Table 21.
1. ST CF does not assert the WAIT signal.
2. -IOIS16 is not supported in this mode.
5.4
Figure 8.
1. The device addresses consists of −CS0, −CS1, and A2-A0.
2. The Data I/O consist of D15-D0 (16-bit) or D7-D0 (8 bit).
3. −IOCS16 is shown for PIO modes 0, 1 and 2. For other modes, this signal is ignored.
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thCE(IOWR)
tsuREG(IOWR) t
thREG(IOWR)
tdfIOIS16(A)
tdrIOIS16(A)
Symbol
A0-A2, −CS0, −CS1
Read Data D0-D15
Write Data D0-D15
−IORD/−IOWR
−IOCS16
I/O Write timing
True IDE mode
The timing waveforms for True IDE mode and True IDE DMA mode of operation in this
section are drawn using the conventions in the ATA-4 specification, which are different than
the conventions used in the PCMCIA specification and earlier versions of this specification.
Signals are shown with their asserted state as High regardless of whether the signal is
actually negative or positive true. Consequently, the -IORD, the -IOWR and the -IOCS16
signals are shown in the waveforms inverted from their electrical states on the bus.
True IDE PIO mode Read/Write waveforms
t
t
t
t
Symbol
IWHEH
RGLIWL
IWHRGH
AVISL
AVISH
IEEE
Cycle Time Mode
(2)
(1)
(2)
(3)
CE Hold following IOWR
REG Setup before IOWR
REG Hold following IOWR
IOIS16 Delay Falling from
Address
IOIS16 Delay Rising from
Address
(1)
(continued)
t7
Parameter
t1
ADDRESS VALID
t0
Min Max Min Max Min Max Min Max
20
5
0
250ns
35
35
t2
20
5
0
120ns
t3
t5
NA
NA
(2)
(2)
VALID
VALID
10
5
0
t4
t6
100ns
t6z
t9
NA
NA
(2)
(2)
t2i
10
5
0
t8
80ns
SMCxxxBF
NA
NA
(2)
(2)
ai10086b
Unit
ns
ns
ns