K9F1G08U0A SAMSUNG [Samsung semiconductor], K9F1G08U0A Datasheet - Page 29

• Manufacturer Part Number: K9F1G08U0A
• Description: 128M x 8 Bit / 256M x 8 Bit NAND Flash Memory
• Manufacturer: SAMSUNG [Samsung semiconductor]

K9F1G08R0A
K9F1G08U0A
Device Operation
PAGE READ
Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command
is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data
within the selected page are transferred to the data registers in less than 25µs(t
this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the data registers, they may be read
out in 30ns cycle time(50ns with 1.8V device) by sequentially pulsing RE. The repetitive high to low transitions of the RE clock make
the device output the data starting from the selected column address up to the last column address.
The device may output random data in a page instead of the consecutive sequential data by writing random data output command.
The column address of next data, which is going to be out, may be changed to the address which follows random data output com-
mand. Random data output can be operated multiple times regardless of how many times it is done in a page.
Figure 6. Read Operation
I/Ox
CLE
CE
WE
ALE
R/B
RE
00h
K9K2G08U1A
Col Add1,2 & Row Add1,2
Address(4Cycle)
30h
Data Field
t
R
29
Spare Field
R
). The system controller can detect the completion of
Data Output(Serial Access)
FLASH MEMORY