MT54W1MH36B-4 MICRON [Micron Technology], MT54W1MH36B-4 Datasheet
MT54W1MH36B-4
Related parts for MT54W1MH36B-4
MT54W1MH36B-4 Summary of contents
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... MT54W4MH9B The read port has dedicated data outputs to support MT54W2MH18B READ operations. The write port has dedicated data MT54W1MH36B inputs to support WRITE operations. This architecture eliminates the need for high-speed bus turnaround. F Access to each port is accomplished using a common address bus ...
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GENERAL DESCRIPTION (continued) Since data can be transferred into and out of the device on every rising edge of both clocks (K and K#, C and C#), memory bandwidth is maximized while sys- tem design is simplified by eliminating bus ...
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READ/WRITE OPERATIONS (continued) WRITE cycles are initiated by W# LOW at K rising edge. The address for the WRITE cycle is provided at the following K# rising edge. Data is expected at the rising edge of K and K#, beginning ...
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CLOCK CONSIDERATIONS This device utilizes internal delay-locked loops for maximum output data valid window. It can be placed into a stopped-clock state to minimize power with a modest restart time of 1,024 clock cycles. Circuitry automatically resets the DLL when ...
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MEG x 8 BALL ASSIGNMENT (TOP VIEW) 165-BALL FBGA CQ / ...
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MEG x 9 BALL ASSIGNMENT (TOP VIEW) 165-BALL FBGA CQ / ...
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MEG x 18 BALL ASSIGNMENT (TOP VIEW) 165-BALL FBGA CQ / D10 C NC D11 Q10 Q11 E NC Q12 D12 F ...
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MEG x 36 BALL ASSIGNMENT (TOP VIEW) 165-BALL FBGA CQ NC/SA SS/ Q27 Q18 D18 B D27 Q28 D19 C D28 D20 Q19 D Q29 D29 Q20 E Q30 Q21 D21 F ...
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FBGA BALL DESCRIPTIONS SYMBOL TYPE SA Input Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K for READ cycles and K# for WRITE cycles. See Ball Assignment figures ...
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FBGA BALL DESCRIPTIONS (continued) SYMBOL TYPE Q_ Output Synchronous Data Outputs: Output data is synchronized to the respective C and and K# rising edges if C and C# are tied HIGH. This bus operates in response ...
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LOAD NEW READ ADDRESS always LOAD NEW WRITE ADDRESS always AT K# NOTE: 1. The address is concatenated with one additional internal LSB to facilitate burst operation. The address order is always fixed as xxx . . . xxx + ...
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TRUTH TABLE Notes 1-6 OPERATION WRITE Cycle: Load address, input write data on consecutive K and K# rising edges READ Cycle: Load address, output data on consecutive C and C# rising edges NOP: No operation STANDBY: Clock stopped BYTE WRITE ...
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ABSOLUTE MAXIMUM RATINGS* Voltage on V Supply DD Relative to V ........................................ 0.5V to +2.8V SS Voltage Supply DD Relative to V ....................................... -0. ..................................................... -0. Storage Temperature ..............................-55ºC to ...
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I OPERATING CONDITIONS AND MAXIMUM LIMITS DD 0ºC £ T £ +70º MAX unless otherwise noted DD A DESCRIPTION CONDITIONS Operating Supply All inputs £ V Current: DDR Cycle time Outputs open Standby Supply t KHKH = Current: ...
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AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS 0ºC £ T £ +70ºC; +1.7V £ V £ +1. DESCRIPTION SYMBOL Clock Clock cycle time t KHKH 4 (K, K#, C, C#) Clock phase jitter ...
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AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS 0ºC £ T £ +70ºC; +1.7V £ V £ +1. DESCRIPTION SYMBOL Hold Times K rising edge to address t KHAX 8 hold K rising edge ...
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AC TEST CONDITIONS Input pulse levels . . . . . . . . . . . . . . . . . . 0.25V to 1.25V Input rise and fall times . . . . . . . . ...
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READ WRITE READ KHKL t KLKH IVKH W# (Note AVKH t KHAX t AVKH t KHAX D D10 D11 D30 t DVKH Q t KHCH t ...
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IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) The QDR SRAM incorporates a serial boundary scan test access port (TAP). This port operates in accor- dance with IEEE Standard 1149.1-2001. The TAP oper- ates using JEDEC-standard 1.8V I/O logic levels. The SRAM ...
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Figure 8 TAP Controller Block Diagram Bypass Register 2 Selection Instruction Register TDI Circuitry Identification Register Boundary Scan Register TCK TAP CONTROLLER TMS NOTE ...
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TDI and TDO balls. To execute the instruction once it is shifted in, the TAP controller needs to be moved into the Update-IR state. EXTEST The EXTEST instruction allows circuitry external to the component package to ...
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Test Clock (TCK) Test Mode Select (TMS) Test Data-In (TDI) Test Data-Out (TDO) TAP DC ELECTRICAL CHARACTERISTICS 0ºC £ T £ +70ºC; +1.7V £ V £ +1. DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock ...
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TAP AC TEST CONDITIONS Input pulse levels . . . . . . . . . . . . . . . . . . . . . V Input rise and fall times . . . . . . ...
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IDENTIFICATION REGISTER DEFINITIONS INSTRUCTION FIELD ALL DEVICES REVISION NUMBER (31:28) DEVICE ID (28:12) 00def0Wx0t0q0b0s0 def = 001 for 36Mb density MICRON JEDEC ID CODE 00000101100 (11:1) ID Register Presence Indicator (0) SCAN REGISTER SIZES REGISTER NAME BIT SIZE (x18) Instruction ...
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BOUNDARY SCAN (EXIT) ORDER BIT# FBGA BALL 11P 11 10P 12 10N 10M 15 11N ...
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SEATING PLANE C 0.12 C 165X 0.45 SOLDER BALL DIAMETER REFERS TO POST REFLOW BALL A11 CONDITION. THE PRE- REFLOW DIAMETER IS Ø 0.40 14.00 7.00 ±0.05 5.00 ±0.05 15.00 ±0.10 NOTE: 1. All dimensions are in millimeters. ...
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REVISION HISTORY • Rev. A, Pub. 9/02..........................................................................................................................................................9/02 • New ADVANCE data sheet 36Mb: 1. HSTL, QDRIIb2 SRAM DD MT54W2MH18B_A.fm - Rev 9/02 4 MEG MEG MEG x 18, 1 MEG x 36 ...