MT54W1MH36B-4 MICRON [Micron Technology], MT54W1MH36B-4 Datasheet - Page 2

• Manufacturer Part Number: MT54W1MH36B-4
• Manufacturer: MICRON [Micron Technology]

GENERAL DESCRIPTION (continued)
device on every rising edge of both clocks (K and K#, C
and C#), memory bandwidth is maximized while sys-
tem design is simplified by eliminating bus turn-
arounds.
for each port (read R#, write W#), which are received at
K rising edge. Port selects permit independent port
operation.
trolled by the K or K# input clock rising edges. Active
LOW byte writes (BWx#) permit byte or nibble write
selection. Write data and byte writes are registered on
the rising edges of both K and K#. The addressing
within each burst of two is fixed and sequential, begin-
ning with the lowest and ending with the highest
address. All synchronous data outputs pass through
output registers controlled by the rising edges of the
output clocks (C and C# if provided, otherwise K and
K#).
ties: test mode select (TMS), test data-in (TDI), test
clock (TCK), and test data-out (TDO). JTAG circuitry is
used to serially shift data to and from the SRAM. JTAG
inputs use JEDEC-standard 1.8V I/O levels to shift data
during this testing mode of operation.
NOTE:
36Mb: 1.8V V
MT54W2MH18B_A.fm - Rev 9/02
D (Data In)
1. The functional block diagram illustrates simplified device operation. See truth table, ball descriptions, and timing diagrams for
2. n = 20
ADDRESS
Since data can be transferred into and out of the
Depth expansion is accomplished with port selects
All synchronous inputs pass through registers con-
Four balls are used to implement JTAG test capabili-
detailed information. The x8, x9, and x36 operations are the same, with apporpriate adjustments of depth and width.
BW0#
BW1#
W#
DD
R#
K#
K#
K
K
, HSTL, QDRIIb2 SRAM
W#
R#
18
n
REGISTRY
REGISTRY
ADDRESS
& LOGIC
& LOGIC
DATA
36
n
Functional Block Diagram: 2 Meg x 18
K
W
R
T
E
I
G
R
E
2
4 MEG x 8, 4 MEG x 9, 2 MEG x 18, 1 MEG x 36
W
R
T
E
I
D
R
V
E
R
I
Figure 2
MEMORY
2 x 36
ARRAY
n
2
all inputs and outputs are HSTL-compatible. The
device is ideally suited for applications that benefit
from a high-speed, fully-utilized DDR data bus.
sramds) for the latest data sheet.
READ/WRITE OPERATIONS
burst of two data, requiring one full clock cycle of bus
utilization. The resulting benefit is that short data
transactions can remain in operation on both buses
provided that the address rate can be maintained by
the system (2x the clock frequency).
by asserting R# LOW at K rising edge. Data is delivered
after the rising edge of K# (t + 1) using C and C# as the
output timing references or using K and K#, if C and C#
are tied HIGH. If C and C# are tied HIGH, they may not
be toggled during device operation. Output tri-stating
is automatically controlled such that the bus is
released if no data is being delivered. This permits
banked SRAM systems with no complex OE timing
generation. Back-to-back READ cycles are initiated
every K rising edge.
The SRAM operates from a +1.8V power supply, and
Please refer to Micron’s Web site
All bus transactions operate on an uninterruptable
READ cycles are pipelined. The request is initiated
1.8V V
N
S
E
S
E
M
Micron Technology, Inc., reserves the right to change products or specifications without notice.
A
P
S
MUX
DD
, HSTL, QDRIIb2 SRAM
36
C
R
G
A
E
O
U
U
T
P
T
K, K#
C, C#
or
36
O
U
U
T
P
T
(www.micron.com/
C
S
E
L
E
T
O
U
U
T
P
T
©2002, Micron Technology Inc.
U
B
F
F
E
R
(Echo Clock Out)
ADVANCE
18
(Data Out)
2
CQ, CQ#
Q