PPC405EP-3GB133CZ AMCC [Applied Micro Circuits Corporation], PPC405EP-3GB133CZ Datasheet - Page 34
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PPC405EP-3GB133CZ
Manufacturer Part Number
PPC405EP-3GB133CZ
Description
PowerPC 405EP Embedded Processor
Manufacturer
AMCC [Applied Micro Circuits Corporation]
Datasheet
1.PPC405EP-3GB133CZ.pdf
(50 pages)
PPC405EP – PowerPC 405EP Embedded Processor
Table 6. Signal Functional Description (Sheet 4 of 6)
Secondary multiplexed signals are shown in brackets.
Notes:
1. Receiver input has hysteresis.
2. Must pull up. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
3. Must pull down. See “Pull-Up and Pull-Down Resistors” on page 29 for recommended termination values.
4. If not used, must pull up.
5. If not used, must pull down.
6. Strapping input during reset; pull up or pull down as required.
7. Pull-up may be required. See “External Bus Control Signals” on page 30.
34
Internal Peripheral Interface
Interrupts Interface
JTAG Interface
[UART0_DCD]
[UART0_DSR]
[UART0_DTR]
Signal Name
UART0_CTS
UART0_RTS
[UART1_Rx]
[UART1_Tx]
[UART0_RI]
UART0_Rx
UART0_Tx
[PerBLast]
PerReady
ExtReset
[IRQ0:6]
IICSCL
IICSDA
PerClk
TMS
TDI
Ready to transfer data.
Used to indicates the last transfer of a memory access.
To access this function, software must toggle a DCR bit.
Peripheral clock to be used by peripheral slaves.
Peripheral reset to be used by peripheral slaves.
UART0 Serial Data In.
UART0 Serial Data Out.
UART0 Data Carrier Detect.
To access this function, software must toggle a DCR bit.
UART0 Data Set Ready.
To access this function, software must toggle a DCR bit.
UART0 Clear To Send.
UART0 Data Terminal Ready.
To access this function, software must toggle a DCR bit.
UART0 Request To Send.
UART0 Ring Indicator.
To access this function, software must toggle a DCR bit.
UART1 Serial Data In.
To access this function, software must toggle a DCR bit.
UART1 Serial Data Out.
To access this function, software must toggle a DCR bit.
IIC Serial Clock.
IIC Serial Data.
Interrupt requests
To access this function, software must toggle a DCR bit.
Test data in.
JTAG test mode select.
Description
Revision 1.07 – September 10, 2007
I/O
I/O
I/O
I/O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
3.3V LVTTL
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
5V tolerant
3.3V IIC
3.3V IIC
Type
Data Sheet
Notes
1, 7
1, 2
1, 2
1, 4
1, 4
1
1
6
1
1
1
6
1
1
1
AMCC