PPC405EX-NPAFFFTX AMCC [Applied Micro Circuits Corporation], PPC405EX-NPAFFFTX Datasheet - Page 58

• Manufacturer Part Number: PPC405EX-NPAFFFTX
• Description: PowerPC 405EX Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

PPC405EX – PowerPC 405EX Embedded Processor
DDR 1/2 SDRAM I/O Specifications
The DDR SDRAM controller times its operation using the internal PLB clock signal and generates MemClkOut from
the PLB clock. The PLB clock is an internal signal that cannot be directly observed. However MemClkOut is the
same frequency as the PLB clock signal and is in phase with the PLB clock signal.
Note: MemClkOut can be advanced with respect to the PLB clock by means of the SDRAM0_CLKTR
The signals are terminated as indicated in Figure 6 for the DDR timing data in the following sections.
Board Layout Restrictions
TBP
Clocking
TBP
Figure 6. DDR SDRAM Simulation Signal Termination Model
DDR2 SDRAM On-Die Termination Impedance Setting
For all DDR2 applications, the On-Die Termination (ODT) impedance value must be set to 75 ohms in the DIMM
Extended Mode Register (EMR) in order to optimize the data transmission during memory write operations.
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Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data.
programming register. In a typical system, users advance MemClkOut by 90°. This depends on the specific
application and requires a thorough understanding of the memory system in general (refer to the DDR
SDRAM Controller chapter in the PPC405EX Embedded Processor User’s Manual).
It is not a recommended physical circuit design for this interface. An actual interface design will depend on many
factors, including the type of memory used and the board layout.
PPC405EX
Addr/Ctrl (DDR2)
Addr/Ctrl/Data/DQS/DM (DDR1)
MemClkOut
MemClkOut
10pF
10pF
V
120Ω
TT
Preliminary Data Sheet
50Ω
30pF
Revision 1.09 - August 21, 2007
= SOV
DD
/2
AMCC Proprietary