PEEL18LV8ZP-25L ANACHIP [Anachip Corp], PEEL18LV8ZP-25L Datasheet - Page 5
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PEEL18LV8ZP-25L
Manufacturer Part Number
PEEL18LV8ZP-25L
Description
CMOS Programmable Electrically Erasable Logic Device
Manufacturer
ANACHIP [Anachip Corp]
Datasheet
1.PEEL18LV8ZP-25L.pdf
(10 pages)
switching long enough to trigger the next power-down.
(Note that the tPD is approximately 5 ns. slower on the first
transition from sleep mode.)
As a result of the "Zero-Power" feature, significant power
savings can be realized for combinatorial or sequential
operations when the inputs or clock change at a modest
rate. See Figure 6.
Anachip Corp.
www.anachip.com.tw
10
11
12
#
1
2
3
4
5
6
7
8
9
Configuration
A
0
1
0
1
0
1
0
1
0
1
0
1
Figure 5 - Equivalent Circuits for the twelve configurations of the PEEL18LV8Z I/O Macrocell
B
0
0
1
1
0
0
1
1
0
0
1
1
C
1
1
0
0
1
1
1
1
0
0
1
1
D
0
0
0
0
1
1
1
1
0
0
0
0
Bi-directional I/O
Combinatorial Feedback
Register Feedback
Input/Feedback Select
5/10
When the PEEL18LV8Z is powered up, a built-in feature
holds the outputs in tri-state until Vcc reaches 2.2V. This
prevents output transitions during power-up.
Combinatorial
Combinatorial
Combinatorial
Register
Register
Register
Output Select
Rev. 1.0 Dec 16, 2004
Active High
Active High
Active High
Active High
Active High
Active High
Active Low
Active Low
Active Low
Active Low
Active Low
Active Low