M366S6453CTS-L1H/C1H SAMSUNG [Samsung semiconductor], M366S6453CTS-L1H/C1H Datasheet - Page 10

• Manufacturer Part Number: M366S6453CTS-L1H/C1H
• Description: PC133/PC100 Unbuffered DIMM
• Manufacturer: SAMSUNG [Samsung semiconductor]

M366S6453CTS
M366S6453CTS-L7C/L7A/L1H/L1L, C7C/C7A/C1H/C1L
• Organization : 64MX64
• Composition : 32MX8 *16
• Used component part # : K4S560832C-TL7C/7A/1H/1L,TC7C/7A/1H/1L
• # of rows in module : 2row
• # of banks in component : 4 banks
• Feature : 1,375 mil height & double sided component
• Refresh : 8K/64ms
• Contents :
Byte#.
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
0
1
2
3
4
5
6
7
8
9
# of bytes written into serial memory at module manufacturer
Total # of bytes of SPD memory device
Fundamental memory type
# of row address on this assembly
# of column address on this assembly
# of module Rows on this assembly
Data width of this assembly
...... Data width of this assembly
Voltage interface standard of this assembly
SDRAM cycle time from clock @CAS latency of 3
SDRAM access time from clock @CAS latency of 3
DIMM configuration type
Refresh rate & type
Primary SDRAM width
Error checking SDRAM width
Minimum clock delay for back-to-back random column
SDRAM device attributes : Burst lengths supported
SDRAM device attributes : # of banks on SDRAM device
SDRAM device attributes : CAS latency
SDRAM device attributes : CS latency
SDRAM device attributes : Write latency
SDRAM module attributes
SDRAM device attributes : General
SDRAM cycle time @CAS latency of 2
SDRAM access time @CAS latency of 2
SDRAM cycle time @CAS latency of 1
SDRAM access time @CAS latency of 1
Minimum row precharge time (=t
Minimum row active to row active delay (t
Minimum RAS to CAS delay (=t
Minimum activate precharge time (=t
Module Row density
Command and Address signal input setup time
Command and Address signal input hold time
Data signal input setup time
Function described
RCD
RP
)
)
RAS
)
RRD
)
7.5ns
5.4ns
7.5ns
5.4ns
1.5ns
0.8ns
1.5ns
Non-buffered/Non-Registered &
15ns
15ns
15ns
45ns
7.8us, support self refresh self
-7C
precharge all, auto precharge
Burst Read Single bit Write
+/- 10% voltage tolerance,
redundant addressing
Function Supported
1, 2, 4, 8 & full page
256bytes (2K-bit)
2 Row of 256MB
7.5ns
5.4ns
1.5ns
0.8ns
1.5ns
10ns
20ns
15ns
20ns
45ns
t
-7A
6ns
CCD
Non parity
PC133/PC100 Unbuffered DIMM
128bytes
SDRAM
4 banks
64 bits
LVTTL
2 Row
0 CLK
0 CLK
None
2 & 3
13
10
x8
= 1CLK
-
-
-
10ns
10ns
20ns
20ns
20ns
50ns
-1H
6ns
6ns
2ns
1ns
2ns
10ns
12ns
20ns
20ns
20ns
50ns
6ns
7ns
2ns
1ns
2ns
-1L
2Dh
75h
54h
75h
54h
0Fh
0Fh
0Fh
15h
08h
15h
-7C
REV. 0.0 Sept. 2001
A0h
2Dh
75h
54h
60h
14h
0Fh
14h
15h
08h
15h
-7A
Hex value
0Dh
0Ah
0Eh
80h
08h
04h
02h
40h
00h
01h
00h
82h
08h
00h
01h
8Fh
04h
06h
01h
01h
00h
00h
00h
40h
A0h
A0h
-1H
60h
60h
14h
14h
14h
32h
20h
10h
20h
C0h
A0h
60h
70h
14h
14h
14h
32h
20h
10h
20h
-1L
Note
1
1
2
2
2
2
2
2