K9F4G08U0A SAMSUNG [Samsung semiconductor], K9F4G08U0A Datasheet
K9F4G08U0A
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... K9K8G08U1A K9F4G08U0A K9XXG08UXA INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. ...
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... K9K8G08U1A K9F4G08U0A Document Title 512M x 8 Bit / Bit NAND Flash Memory Revision History Revision No History 0.0 1. Initial issue 0.1 1. Leaded part is eliminated 2. tRHW is defined The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near your office ...
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... Serial Access : 25ns(Min.) GENERAL DESCRIPTION Offered in 512Mx8bit, the K9F4G08U0A is a 4G-bit NAND Flash Memory with spare 128M-bit. Its NAND cell provides the most cost- effective solution for the solid state application market. A program operation can be performed in typical 200µs on the (2K+64)Byte page and an erase operation can be performed in typical 1 ...
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... ALE N.C 20 N.C 21 N.C 22 N.C 23 N.C 24 PACKAGE DIMENSIONS 48-PIN LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE( TSOP1 - 1220F #1 #24 0~8° 0.45~0.75 0.018~0.030 K9F4G08U0A-PCB0/PIB0 48-pin TSOP1 38 37 Standard Type 36 35 12mm x 20mm ...
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... K9K8G08U1A K9F4G08U0A PIN CONFIGURATION (ULGA / CLE PACKAGE DIMENSIONS 52-ULGA (measured in millimeters) Top View 12.00±0.10 #A1 K9F4G08U0A-ICB0/IIB0 / Vcc NC Vss IO7 IO5 Vcc R/B NC IO6 IO4 NC NC ...
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... K9K8G08U1A K9F4G08U0A /CE1 4 3 CLE1 PACKAGE DIMENSIONS 52-ULGA (measured in millimeters) Top View 12.00±0.10 #A1 K9K8G08U1A-ICB0/IIB0 /RE1 R/B2 IO7-2 NC IO6-2 IO5-2 Vcc /RE2 Vss IO7-1 IO5-1 Vcc R/B1 /WP2 IO6-1 IO4-1 /CE2 ...
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... K9K8G08U1A K9F4G08U0A PIN DESCRIPTION Pin Name DATA INPUTS/OUTPUTS I/O ~ I/O The I/O pins are used to input command, address and data, and to output data during read operations. The pins float to high-z when the chip is deselected or when the outputs are disabled. COMMAND LATCH ENABLE CLE The CLE input controls the activating path for commands sent to the command register ...
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... K9K8G08U1A K9F4G08U0A Figure 1. K9F4G08U0A Functional Block Diagram X-Buffers Latches & Decoders Y-Buffers Latches & Decoders Command Command Register CE Control Logic RE & High Voltage WE Generator CLE ALE Figure 2. K9F4G08U0A Array Organization 256K Pages (=4,096 Blocks) 2K Bytes ...
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... The memory array con- sists of 4,096 separately erasable 128K-byte blocks. It indicates that the bit by bit erase operation is prohibited on the K9F4G08U0A. The K9F4G08U0A has addresses multiplexed into 8 I/Os. This scheme dramatically reduces pin counts and allows system upgrades to future densities by maintaining consistency in system board design ...
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... K9K8G08U1A K9F4G08U0A ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to VSS K9XXG08UXA-XCB0 Temperature Under Bias K9XXG08UXA-XIB0 K9XXG08UXA-XCB0 Storage Temperature K9XXG08UXA-XIB0 Short Circuit Current NOTE : 1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins ...
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... The 1st block, which is placed on 00h block address, is guaranteed valid block program/erase cycles with 1bit/512Byte ECC. 3. The number of valid block is on the basis of single plane operations, and this may be decreased with two plane operations Each K9F4G08U0A chip in the K9K8G08U1A has Maximun 80 invalid blocks. AC TEST CONDITION (K9XXG08UXA-XCB0 : 70° ...
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... K9K8G08U1A K9F4G08U0A Program / Erase Characteristics Parameter Program Time Dummy Busy Time for Two-Plane Page Program Number of Partial Program Cycles Block Erase Time NOTE : 1. Typical value is measured at Vcc=3.3V Typical program time is defined as the time within which more than 50% of the whole pages are programmed at 3.3V Vcc and 25 ...
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... K9K8G08U1A K9F4G08U0A AC Characteristics for Operation Parameter Data Transfer from Cell to Register ALE to RE Delay CLE to RE Delay Ready to RE Low RE Pulse Width WE High to Busy Read Cycle Time RE Access Time CE Access Time RE High to Output Hi-Z CE High to Output Hi-Z RE High to Output Hold RE Low to Output Hold ...
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... K9K8G08U1A K9F4G08U0A NAND Flash Technical Notes Initial Invalid Block(s) Initial invalid blocks are defined as blocks that contain one or more initial invalid bits whose reliability is not guaranteed by Samsung. The information regarding the initial invalid block(s) is called the initial invalid block information. Devices with initial invalid block(s) have the same quality level as devices with all valid blocks and have the same AC and DC characteristics ...
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... K9K8G08U1A K9F4G08U0A NAND Flash Technical Notes Error in write or read operation Within its life time, additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read fail- ure after erase or program, block replacement should be done ...
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... K9K8G08U1A K9F4G08U0A NAND Flash Technical Notes Erase Flow Chart Start Write 60h Write Block Address Write D0h Read Status Register I R Yes * No Erase Error I Yes Erase Completed * : If erase operation results in an error, map out the failing block and replace it with another block. ...
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... EDC, the copy-back program operation could also accumulate bit errors. K9F4G08U0A supports copy-back with EDC to prevent cumulative bit errors. To make EDC valid, the page program operation should be performed on either whole page(2112byte) or sector(528byte). Modifying the data of a sector by Random Data Input before Copy-Back Program must be performed for the whole sector and is allowed only once per each sector ...
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... K9K8G08U1A K9F4G08U0A System Interface Using CE don’t-care. For an easier system interface, CE may be inactive during the data-loading or serial access as shown below. The internal 2,112byte data registers are utilized as separate buffers for this operation and the system design gets more flexible. In addition, for voice or audio applications which use slow cycle time on the order of µ ...
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... K9K8G08U1A K9F4G08U0A NOTE I/O Device I/Ox K9F4G08U0A I I/O 7 Command Latch Cycle CLE CE WE ALE I/Ox Address Latch Cycle t CLS CLE ALS ALE t DS I/Ox Col. Add1 DATA Data In/Out Col. Add1 Col. Add2 2,112byte A0~A7 A8~A11 t t CLS CLH ...
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... K9K8G08U1A K9F4G08U0A Input Data Latch Cycle CLE ALE t ALS I/Ox DIN 0 * Serial Access Cycle after Read I/ R/B NOTES : Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRLOH is valid when frequency is higher than 33MHz. ...
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... K9K8G08U1A K9F4G08U0A Serial Access Cycle after Read REH RE t REA t CEA I/ R/B NOTES : Transition is measured at ±200mV from steady state voltage with load. This parameter is sampled and not 100% tested. tRLOH is valid when frequency is higher than 33MHz. tRHOH starts to be valid when frequency is lower than 33MHz. ...
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... K9K8G08U1A K9F4G08U0A Read Operation CLE ALE RE I/Ox 00h Col. Add1 Col. Add2 Row Add1 Column Address R/B Read Operation (Intercepted by CE) CLE CE WE ALE RE I/Ox 00h Col. Add1 Col. Add2 Column Address R/B t CLR 30h Row Add2 Row Add3 ...
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... K9K8G08U1A K9F4G08U0A FLASH MEMORY 23 Preliminary ...
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... K9K8G08U1A K9F4G08U0A Page Program Operation CLE ALE RE I/Ox 80h Co.l Add1 Col. Add2 Row Add1 SerialData Column Address Input Command R/B NOTES : tADL is the time from the WE rising edge of final address cycle to the WE rising edge of first data cycle ADL Din ...
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... K9K8G08U1A K9F4G08U0A FLASH MEMORY ≈ ≈ ≈ ≈ ≈ ≈ 25 Preliminary ≈ ...
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... K9K8G08U1A K9F4G08U0A FLASH MEMORY ≈ ≈ ≈ ≈ 26 Preliminary ...
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... K9K8G08U1A K9F4G08U0A Block Erase Operation CLE ALE RE I/Ox 60h Row Add1 Row Add2 Row Add3 Row Address R/B Auto Block Erase Setup Command t t BERS WB D0h Busy Erase Command 27 Preliminary FLASH MEMORY t WHR 70h I/O 0 I/O =0 Successful Erase 0 Read Status I/O =1 Error in Erase ...
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... K9K8G08U1A K9F4G08U0A ≈ ≈ FLASH MEMORY ≈ ≈ ≈ ≈ ≈ ≈ 28 Preliminary ...
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... K9K8G08U1A K9F4G08U0A FLASH MEMORY 29 Preliminary ...
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... Address 1cycle Device Device Code (2nd Cycle) K9F4G08U0A DCh K9K8G08U1A REA Device 00h ECh Code Maker Code Device Code 3rd Cycle 10h Same as each K9F4G08U0A Preliminary FLASH MEMORY 3rd cyc. 4th cyc. 5th cyc. 4th Cycle 5th Cycle 95h 54h ...
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... K9K8G08U1A K9F4G08U0A ID Definition Table Access command = 90H Description 1 st Byte Maker Code 2 Byte nd Device Code 3 Byte Internal Chip Number, Cell Type, Number of Simultaneously Programmed Pages, Etc rd 4 Byte Page Size, Block Size,Redundant Area Size, Organization, Serial Access Minimum th Plane Number, Plane Size ...
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... K9K8G08U1A K9F4G08U0A 5th ID Data Description 1 2 Plane Number 4 8 64Mb 128Mb 256Mb Plane Size 512Mb (w/o redundant Area) 1Gb 2Gb 4Gb 8Gb Reserved FLASH MEMORY I/O7 I/O6 I/O5 I/O4 I/O3 I/ Preliminary I/O1 I/ ...
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... K9K8G08U1A K9F4G08U0A Device Operation PAGE READ Page read is initiated by writing 00h-30h to the command register along with five address cycles. After initial power up, 00h command is latched. Therefore only five address cycles and 30h command initiates that operation after initial power up. The 2,112 bytes of data within the selected page are transferred to the data registers in less than 20µ ...
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... K9K8G08U1A K9F4G08U0A Figure 7. Random Data Output In a Page R/B RE Address I/Ox 00h 30h 5Cycles Col. Add.1,2 & Row Add.1,2,3 PAGE PROGRAM The device is programmed basically on a page basis, but it does allow multiple partial page programming of a word or consecutive bytes up to 2,112 single page program cycle. The number of consecutive partial page programming operation within the same page without an intervening erase operation must not exceed 4 times for a single page ...
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... K9K8G08U1A K9F4G08U0A Figure 9. Random Data Input In a Page R/B I/Ox 80h Address & Data Input Col. Add.1,2 & Row Add1,2,3 Data Note: 1. For EDC operation, only one time random data input is possible at the same address. Copy-Back Program The Copy-Back program is configured to quickly and efficiently rewrite data stored in one page without utilizing an external memory. ...
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... K9K8G08U1A K9F4G08U0A EDC OPERATION Note that for the user who use Copy-Back with EDC mode, only one time random data input is possible at the same address during Copy-Back program or page program mode. For the user who use Copy-Back without EDC, there is no limitation for the random data input at the same address. Figure 12. Page Copy-Back Program Operation with EDC & ...
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... K9K8G08U1A K9F4G08U0A Figure 14. Two-Plane Page Program R/B I 80h Address & Data Input Valid Fixed ’Low’ Fixed ’Low’ Fixed ’Low’ NOTE : noticeable that same row address except for A 2. Any command between 11h and 81h is prohibited except 70h and FFh. ...
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... K9K8G08U1A K9F4G08U0A Two-Plane Copy-Back Program Two-Plane Copy-Back Program is an extension of Copy-Back Program, for a single plane with 2112 byte page registers. Since the device is equipped with two memory planes, activating the two sets of 2112 byte page registers enables a simultaneous program- ming of two pages. ...
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... K9K8G08U1A K9F4G08U0A Figure 17. Two-Plane Copy-Back Program Operation with Random Data Input R/B I/Ox Add.(5Cycles) 00h 35h Col. Add.1,2 & Row Add.1,2,3 Source Address On Plane0 R/B I/Ox Add.(5Cycles) 85h Col. Add.1,2 & Row Add.1,2,3 1 Destination Address Valid Fixed ’Low’ Fixed ’ ...
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... K9K8G08U1A K9F4G08U0A READ STATUS The device contains a Status Register which may be read to find out whether program or erase operation is completed, and whether the program or erase operation is completed successfully. After writing 70h command to the command register, a read cycle outputs the content of the Status Register to the I/O pins on the falling edge RE, whichever occurs last. This two line control allows the system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired ...
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... Command is latched t CEA WHR t REA Device ECh 3rd Cyc. Code Maker code Device code 3rd Cycle 4th Cycle 10h Same as each K9F4G08U0A RST Waiting for next command 41 Preliminary FLASH MEMORY 4th Cyc. 5th Cyc. 5th Cycle 95h 54h After Reset ...
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... K9K8G08U1A K9F4G08U0A READY/BUSY The device has a R/B output that provides a hardware method of indicating the completion of a page program, erase and random read completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command regis- ter or random read is started after address loading. It returns to high when the internal controller has finished the operation. The pin is an open-drain driver thereby allowing two or more R/B outputs to be Or-tied ...
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... K9K8G08U1A K9F4G08U0A Data Protection & Power up sequence The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at V during power-up and power-down. A recovery time of minimum 100µs is required before internal circuit gets ready for any command sequences as shown in Figure 21 ...