IXP45X INTEL [Intel Corporation], IXP45X Datasheet - Page 32
IXP45X
Manufacturer Part Number
IXP45X
Description
Product Line of Network Processors
Manufacturer
INTEL [Intel Corporation]
Datasheet
1.IXP45X.pdf
(148 pages)
- Current page: 32 of 148
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Figure 4.
3.2.1
Intel
Datasheet
32
®
IXP45X and Intel
Intel XScale
Super Pipeline
The super pipeline is composed of integer, multiply-accumulate (MAC), and memory
pipes.
The integer pipe has seven stages:
The memory pipe has eight stages:
• JTAG debug unit that uses hardware break points and 256-entry trace history
• Branch Target Buffer (BTB)/Fetch 1
• Fetch 2
• Decode
• Register File/Shift
• ALU Execute
• State Execute
• Integer Writeback
• The first five stages of the Integer pipe (BTB/Fetch 1 through ALU Execute)
• Data Cache 1
• Data Cache 2
• Data Cache Writeback
This PMU is for the Intel XScale
monitoring of internal bus performance.
buffer (for flow-change messages) to debug programs
. . . then finishes with the following memory stages
®
IXP46X Product Line of Network Processors
Coprocessor Interface
Accumulate
Multiply
®
IRQ
FIQ
Technology Block Diagram
Intel
®
IXP45X and Intel
Interrupt
Request
Execution
Management
Core
Instruction
System
Address
Data
Data
®
®
processor only. An additional PMU is supplied for
IXP46X Product Line of Network Processors—Datasheet
Branch Target Cache
Instruction Cache
Mini-Data Cache
Data Cache
Debug/
JTAG
32 Kb
PMU
32 Kb
2 Kb
Document Number:
M
M
M
M
U
U
306261-004US
South
AHB
Bus
August 2006
A9568-01
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