EDD1216AJBG ELPIDA [Elpida Memory], EDD1216AJBG Datasheet - Page 11

• Manufacturer Part Number: EDD1216AJBG
• Description: 128M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Timing Parameter Measured in Clock Cycle
tCK
Parameter
Write to pre-charge command delay
(same bank)
Read to pre-charge command delay
(same bank)
Write to read command delay
(to input all data)
Burst stop command to write
command delay
(CL = 2)
(CL = 2.5)
(CL = 3)
Burst stop command to DQ High-Z
(CL = 2)
(CL = 2.5)
(CL = 3)
Read command to write command
delay (to output all data)
(CL = 2)
(CL = 2.5)
(CL = 3)
Pre-charge command to High-Z
(CL = 2)
(CL = 2.5)
(CL = 3)
Write command to data in latency
Write recovery
DM to data in latency
Self-refresh exit to non-read
command
Self-refresh exit to read command
Power down entry
Power down exit to command input
Active to Precharge command period tRAS
Active to Active/Auto-refresh
command period
Auto-refresh to Active/Auto-refresh
command period
Active to Read/Write delay
Precharge to active command period tRP
Preliminary Data Sheet E1154E10 (Ver. 1.0)
Symbol
tWPD
tRPD
tWRD
tBSTW
tBSTW
tBSTW
tBSTZ
tBSTZ
tBSTZ
tRWD
tRWD
tRWD
tHZP
tHZP
tHZP
tWCD
tWR
tDMD
tSNR
tSRD
tPDEN
tPDEX
tRC
tRFC
tRCD
Number of clock cycle
5ns
min.
4 + BL/2
BL/2
2 + BL/2
—
—
3
—
—
3
—
—
3 + BL/2
—
—
3
1
3
0
15
200
1
1
8
11 (-5B)
12 (-5C)
14
3 (-5B)
4 (-5C)
3 (-5B)
4 (-5C)
11
max.
—
—
—
—
—
—
—
—
3
—
—
—
—
—
3
1
—
0
—
—
1
—
6ns
min.
4 + BL/2
BL/2
2 + BL/2
—
3
3
—
2.5
3
—
3 + BL/2
3 + BL/2
—
2.5
3
1
3
0
12
200
1
1
7
10
12
3
3
max.
—
—
—
—
—
—
—
2.5
3
—
—
—
—
2.5
3
1
—
0
—
—
1
—
7.5ns
min.
3 + BL/2
BL/2
2 + BL/2
2
3
3
2
2.5
3
2 + BL/2
3 + BL/2
3 + BL/2
2
2.5
3
1
2
0
10
200
1
1
6
9
10
3
3
EDD1216AJBG
max.
—
—
—
—
—
—
2
2.5
3
—
—
—
2
2.5
3
1
—
0
—
—
1
—
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK