EDD1216AJBG ELPIDA [Elpida Memory], EDD1216AJBG Datasheet - Page 23

• Manufacturer Part Number: EDD1216AJBG
• Description: 128M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Operation of the DDR SDRAM
Power-up Sequence
(1) Apply power and maintain CKE at an LVCMOS low state (all other inputs are undefined).
(2) Start clock and maintain stable condition for a minimum of 200 µs.
(3) After the minimum 200 µs of stable power and clock (CK, /CK), apply NOP and take CKE high.
(4) Issue precharge all command for the device.
(5) Issue EMRS to enable DLL.
(6) Issue a mode register set command (MRS) for "DLL reset" with bit A8 set to high (An additional 200 cycles of
(7) Issue precharge all command for the device.
(8) Issue 2 or more auto-refresh commands.
(9) Issue a mode register set command to initialize device operation with bit A8 set to low in order to avoid resetting
Preliminary Data Sheet E1154E10 (Ver. 1.0)
Command
Apply VDD before or at the same time as VDDQ.
Apply VDDQ before or at the same time as VTT and VREF.
clock input is required to lock the DLL after every DLL reset).
the DLL.
/CK
CK
PALL
(4)
2 cycles (min.)
DLL enable
EMRS
(5)
2 cycles (min.)
DLL reset with A8 = High
Power-up Sequence after CKE Goes High
(6)
MRS
2 cycles (min.)
PALL
(7)
t
23
RP
200 cycles (min)
REF
REF
(8)
t
RFC
REF
t
RFC
Disable DLL reset with A8 = Low
MRS
(9)
EDD1216AJBG
2 cycles (min.)
command
Any