EDD1232AABH ELPIDA [Elpida Memory], EDD1232AABH Datasheet - Page 33

• Manufacturer Part Number: EDD1232AABH
• Description: 128M bits DDR SDRAM (4M words x 32 bits)
• Manufacturer: ELPIDA [Elpida Memory]

A Write command to the consecutive Read command interval: To complete the burst operation
1. Same
2. Same
3. Different
Command
Data Sheet E0533E50 (Ver. 5.0)
Note: tWTR is referenced from the first positive CK edge after the last desired data in pair tWTR.
Destination row of the consecutive read
command
Bank
address
DQS
/CK
DM
DQ
CK
WRIT
t0
Row address State
Same
Different
Any
in0
t1
ACTIVE
—
ACTIVE
IDLE
BL/2 + 3 cycle
in1
INPUT
tWRD (min)
in2
t2
WRITE to READ Command Interval
Operation
To complete the burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 3) after the write command.
Precharge the bank tWPD after the preceding write command. tRP after the
precharge command, issue the ACT command. tRCDRD after the ACT command,
the consecutive read command can be issued. See ‘A read command to the
consecutive precharge interval’ section.
To complete a burst operation, the consecutive read command should be
performed tWRD (= BL/ 2 + 3) after the write command.
Precharge the bank independently of the preceding write operation. tRP after the
precharge command, issue the ACT command. tRCDRD after the ACT command,
the consecutive read command can be issued.
NOP
in3
t3
33
tWTR*
t4
READ
t5
t6
NOP
EDD1232AABH
t7
out0
OUTPUT
out1
BL = 4
CL = 2
t8
out2
out3
t9