ASC7512 ETC2 [List of Unclassifed Manufacturers], ASC7512 Datasheet - Page 15

• Manufacturer Part Number: ASC7512
• Description: DIGITAL TEMPERATURE SENSOR WITH INTEGRATED FAN CONTROL
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Register 0B-0Eh and 11-14h: ALERT Temperature Limits (Compared to Registers 25h-14h, 26h-15h)
These limits are compared Zone 1 and Zone 2 registers and trigger the optional ALERT signal pin and status bits that may
be enabled in Register 09h, Bit-5. The limits are in binary temperature format representing values from 0 to +127 degrees.
Status Registers
Register 02h: Alert Status Register
The Alert Status Register is a read-only register for reporting the state of the aSC7512’s alarms. It is a read-only register
located at 02h. When any high or low Zone 1 (remote) limits or high or low Zone 2 (local) limits are exceeded, bits 3 through
6 are set accordingly and the ALERT pin 6 will be driven low. If the remote sensor is open-circuit, bit 2 will be set and
the ALERT will be asserted. Reading the status register will re-set these flags if the alerted condition has been removed,
however, the ALERT pin will remain asserted until the master has serviced the SMBus alert. This register is read-only – a
write to this register has no effect.
© Andigilog, Inc. 2006
Register
Address
Register
Address
0Bh
0Ch
0Dh
0Eh
13h
14h
02h
Read/
Read/
Write
Write
R/W
R/W
R/W
R/W
R/W
R/W
3:0
Bit
6
7
R
Zone 2 High Alert
Limit
Zone 2 Low Alert
Limit
Zone 1 High Alert
Limit (MS byte)
Zone 1 High Alert
Limit (LS byte)
Zone 1 Low Alert
Limit (MS byte)
Zone 1 Low Alert
Limit (LS byte)
Alert Status
Register Name
Consecutive
Alert
Reserved
SMBTimeout
Register Name
Name
Table 4 Consecutive Alert Register [22h] bits
R/W
R/W
R/W
R/W
(MSB)
Bit 7
(MSB)
BUSY
Bit 7
7
7
9
1
9
1
Default
Bit 6
LHIGH
000
Bit 6
0
0
6
6
8
0
8
0
www.andigilog.com
The number of consecutive out-of-limit measurements
required to set the ALERT pin.
1: 000
2: 001
3: 011
4: 111
Reserved
Enables a reset of the aSC7512 SMBus interface if it
detects SMBus clock stuck low for more than 35 milli-
seconds.
- 15 -
LLOW
Bit 5
Bit 5
5
5
7
X
7
X
RHIGH
Bit 4
Bit 4
X
X
4
4
6
6
RLOW
Bit 3
Description
Bit 3
X
X
3
3
5
5
ROPEN
Bit 2
Bit 2
2
2
4
X
4
X
Bit 1
Bit 1
RES
August 2006 - 70A05003
X
X
1
1
3
3
aSC7512
(LSB)
(LSB)
Bit 0
RES
Bit 0
X
X
0
0
2
2
Default
Default
Value
Value
55
00
55
00
55
00
00