ASC7512 ETC2 [List of Unclassifed Manufacturers], ASC7512 Datasheet - Page 7

• Manufacturer Part Number: ASC7512
• Description: DIGITAL TEMPERATURE SENSOR WITH INTEGRATED FAN CONTROL
• Manufacturer: ETC2 [List of Unclassifed Manufacturers]

Control Communication
SMBus
The aSC7512 is compatible with devices that are compliant
to the SMBus 2.0 specifications. More information on this
bus can be found at http://www.smbus.org/. Compatibility
of SMBus2.0 to other buses is discussed in the SMBus 2.0
specification.
General Operation
Writing to and reading from the aSC7512 registers is
accomplished via the SMBus-compatible two-wire serial
interface. SMBus protocol requires that one device on the
bus initiate and control all read and write operations. This
device is called the “master” device. The master device
also generates the SCL signal that is the clock signal for all
other devices on the bus. All other devices on the bus are
called “slave” devices. The aSC7512 is a slave device.
Both the master and slave devices can send and receive
data on the bus.
During SMBus operations, one data bit is transmitted per
clock cycle. All SMBus operations follow a repeating nine
clock-cycle pattern that consists of eight bits (one byte) of
transmitted data followed by an acknowledge (ACK) or not
acknowledge (NACK) from the receiving device. Note that
there are no unused clock cycles during any operation—
therefore there must be no breaks in the stream of data
and ACKs / NACKs during data transfers.
For most operations, SMBus protocol requires the SDA line
to remain stable (unmoving) whenever SCL is high — i.e.
any transitions on the SDA line can only occur when SCL is
low. The exceptions to this rule are when the master device
issues a start or stop condition. Note that the slave device
cannot issue a start or stop condition.
SMBus Definitions
The following are definitions for some general SMBus
terms:
Start Condition: This condition occurs when the SDA line
transitions from high to low while SCL is high. The master
device uses this condition to indicate that a data transfer is
about to begin.
Stop Condition: This condition occurs when the SDA line
transitions from low to high while SCL is high. The master
device uses this condition to signal the end of a data
transfer.
Acknowledge and Not Acknowledge: When data are
transferred to the slave device it sends an “acknowledge”
(ACK) after receiving each byte. The receiving device
sends an ACK by pulling SDA low for one clock. Following
the last byte, a master device sends a "not acknowledge"
(NACK) followed by a stop condition. A NACK is indicated
by forcing SDA high during the clock after the last byte.
© Andigilog, Inc. 2006
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Slave Address
aSC7512 is designed to be used primarily in desktop
systems that require only one monitoring device. The
SMBus slave address is fixed at 58 hex (x 1 0 1 1 0 0 0
binary).
Writing to and Reading from the aSC7512
All read and write operations must begin with a start
condition generated by the master device. After the start
condition, the master device must immediately send a
slave address (7-bits) followed by a R/ W bit. If the slave
address matches the address of the aSC7512, it sends an
ACK by pulling the SDA line low for one clock. Read or
write operations may contain one- or two-bytes. See
Figures 2 through 6 for timing diagrams for all aSC7512
operations.
Setting the Register Address Pointer
For all operations, the address pointer stored in the
address pointer register must be pointing to the register
address that is going to be written to or read from. This
register’s content is automatically set to the value of the
first byte following the R/ W bit being set to 0.
After the aSC7512 sends an ACK in response to receiving
the address and R/ W bit, the master device must transmit
an appropriate 8-bit address pointer value as explained in
the Registers section of this data sheet. The aSC7512 will
send an ACK after receiving the new pointer data.
The register address pointer set operation is illustrated in
Figure 2. If the address pointer is not a valid address the
aSC7512 will internally terminate the operation. Also recall
that the address register retains the current address pointer
value between operations. Therefore, once a register is
being pointed to, subsequent read operations do not
require another Address Pointer set cycle.
Writing to Registers
All writes must start with a pointer set as described
previously, even if the pointer is already pointing to the
desired register. The sequence is described in Figure 2.
Immediately following the pointer set, the master must
begin transmitting the data to be written. After transmitting
each byte of data, the master must release the SDA line for
one clock to allow the aSC7512 to acknowledge receiving
the byte. The write operation should be terminated by a
stop condition from the master.
Reading from Registers
To read from a register other than the one currently being
pointed to by the address pointer register, a pointer set
sequence to the desired register must be done as
described previously.
Immediately following the pointer
August 2006 - 70A05003
aSC7512