K6R1008C1D SAMSUNG [Samsung semiconductor], K6R1008C1D Datasheet - Page 3
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K6R1008C1D
Manufacturer Part Number
K6R1008C1D
Description
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges.
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.K6R1008C1D.pdf
(11 pages)
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FUNCTIONAL BLOCK DIAGRAM
K6R1016V1D
FEATURES
• Fast Access Time 8,10ns(Max.)
• Low Power Dissipation
• Single 3.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
• Three State Outputs
• Center Power/Ground Pin Configuration
• Data Byte Control: LB: I/O
• Standard Pin Configuration:
• Operating in Commercial and Industrial Temperature range.
64K x 16 Bit High-Speed CMOS Static RAM(3.3V Operating)
CS
WE
OE
UB
LB
A
A
A
A
A
A
A
A
A
- No Clock or Refresh required
Operating
0
1
2
3
4
5
6
7
8
I/O
Standby (TTL)
I/O
1
9
~I/O
~I/O
8
16
K6R1016V1D-J: 44-SOJ-400
K6R1016V1D-T: 44-TSOP2-400BF
K6R1016V1D-E: 48-TBGA ( 6.0mm X 7.0mm )
(CMOS) :
Clk Gen.
K6R1016V1D- 08: 80mA(Max.)
K6R1016V1D-10: 65mA(Max.)
with 0.75mm ball pitch
: 20mA(Max.)
Cont.
Cont.
Data
Data
Gen.
CLK
5mA(Max.)
1
~ I/O
A
8
9
, UB: I/O
Pre-Charge Circuit
A
128x16 Columns
10
Column Select
Memory Array
I/O Circuit &
A
512 Rows
11
A
9
~ I/O
12
A
13
16
A
14
A
15
- 3 -
GENERAL DESCRIPTION
The K6R1016V1D is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits.
The K6R1016V1D uses 16 common input and output lines and
has at output enable pin which operates faster than address
access time at read cycle. Also it allows that lower and upper
byte access by data byte control (UB, LB). The device is
fabricated using SAMSUNG s advanced CMOS process and
designed for high-speed circuit technology. It is particularly well
suited for use in high-density high-speed system applications.
The K6R1016V1D is packaged in a 400mil 44-pin plastic SOJ
or TSOP2 forward or 48-TBGA.
PIN FUNCTION
I/O
Pin Name
A
1
0
V
N.C
WE
V
CS
OE
UB
LB
~ I/O
- A
CC
SS
15
16
Address Inputs
Write Enable
Chip Select
Output Enable
Lower-byte Control(I/O
Upper-byte Control(I/O
Data Inputs/Outputs
Power(+3.3V)
Ground
No Connection
Pin Function
CMOS SRAM
for AT&T
1
9
~I/O
~I/O
Revision 3.0
8
16
)
June 2002
)