K7R643682M_07 SAMSUNG [Samsung semiconductor], K7R643682M_07 Datasheet - Page 6

• Manufacturer Part Number: K7R643682M_07
• Description: 2Mx36 & 4Mx18 & 8Mx9 QDR II b2 SRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

PIN CONFIGURATIONS
Notes: 1. BW controls write to D0:D8.
PIN NAME
Notes: 1. C, C, K or K cannot be set to V
K7R643682M
K7R641882M
K7R640982M
SYMBOL
A
B
C
D
G
H
K
M
N
R
CQ, CQ
E
F
L
P
J
V
D0-8
Q0-8
V
TMS
TDO
C, C
TCK
K, K
Doff
V
BW
V
TDI
NC
SA
ZQ
2. When ZQ pin is directly connected to V
3. Not connected to chip pad internally.
W
DDQ
REF
R
DD
SS
TDO
Doff
CQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
1K,2K,3K,10K,11K,9K,1L,9L,10L,1M,2M,3M,9M,10M,1N,3N,9N
7A,5A,1B,2B,3B,5B,9B,10B,1C,2C,3C,9C,10C,1D,3D,9D,10D,
11D,1E,2E,9E,1F,2F,3F,9F,10F,11F,1G,9G,10G,11G,1J,2J,3J,9J
2A,3A,9A,10A,4B,8B,5C-7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
V
TCK
NC
NC
NC
NC
NC
NC
NC
NC
SA
D4
D5
Q6
D7
REF
2
11M,11J,10E,11C,2D,2G,3L,2N,10P
11L,10J,11E,11B,3E,3G,2L,3P,11P
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
(TOP VIEW) K7R640982M(8Mx9)
V
SA
NC
NC
NC
NC
NC
NC
NC
NC
Q4
Q5
D6
Q7
SA
DDQ
REF
3
10N,11N,1P,2P,9P
voltage.
PIN NUMBERS
DD
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
11A, 1A
2H,10H
6B, 6A
6P, 6R
V
V
V
V
V
V
V
V
V
V
V
SA
SA
SA
11H
10R
11R
W
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
1H
4A
8A
7B
2R
1R
4
SS
SS
SS
SS
2Mx36 & 4Mx18 & 8Mx9 QDR
V
V
V
V
V
V
V
V
V
NC
NC
SA
SA
SA
SA
5
SS
SS
DD
DD
DD
DD
DD
SS
SS
- 6 -
V
V
V
V
V
V
V
V
V
SA
SA
K
C
C
6
K
SS
SS
SS
SS
SS
SS
SS
SS
SS
V
V
V
V
V
BW
V
V
V
V
NC
SA
SA
SA
SA
7
DD
DD
DD
DD
DD
SS
SS
SS
SS
Nibble Write Control Pin, active when low
Output Driver Impedance Control Input
Output Power Supply (1.5V or 1.8V)
Write Control Pin, active when low
Read Control Pin, active when low
Input Clock for Output Data
V
V
V
V
V
V
V
V
V
V
V
Input Reference Voltage
JTAG Test Mode Select
SA
SA
SA
JTAG Test Data Output
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DLL Disable when low
R
8
Power Supply (1.8 V)
JTAG Test Data Input
SS
SS
SS
SS
Output Echo Clock
JTAG Test Clock
DESCRIPTION
Address Inputs
Data Outputs
No Connect
Data Inputs
Input Clock
Rev. 1.3 March 2007
Ground
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SA
SA
DDQ
9
TM
II b2 SRAM
V
TMS
NC
NC
NC
NC
NC
NC
NC
NC
SA
NC
Q1
D2
D8
10
REF
TDI
NOTE
CQ
NC
NC
NC
NC
NC
Q3
D3
Q2
ZQ
D1
Q0
D0
Q8
11
1
2
3