K7R643682M_07 SAMSUNG [Samsung semiconductor], K7R643682M_07 Datasheet - Page 8

• Manufacturer Part Number: K7R643682M_07
• Description: 2Mx36 & 4Mx18 & 8Mx9 QDR II b2 SRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

Single Clock Mode
Depth Expansion
Separate input and output ports enables easy depth expansion.
Each port can be selected and deselected independently and read and write operation do not affect each other.
Before chip deselected, all read and write pending operations are completed.
Echo clock operation
K7R643682M,K7R641882M and K7R640982M can be operated with the single clock pair K and K, instead of C or C for output
clocks.
To operate these devices in single clock mode, C and C must be tied high during power up
and must be maintained high during operation.
After power up, this device can’t change to or from single clock mode.
Programmable Impedance Output Buffer Operation
K7R643682M,K7R641882M and K7R640982M utilizes internal DLL (Delay-Locked Loops) for maximum output data valid window.
It can be placed into a stopped-clock state to minimize power with a modest restart time of 1024 clock cycles.
Circuitry automatically resets the DLL when absence of input clock is detected.
Power-Up/Power-Down Supply Voltage Sequencing
The following power-up supply voltage application is recommended: V
simultaneously, as long as V
removal sequence is recommended: V
does not exceed V
The designer can program the SRAM's output buffer impedance by terminating the ZQ pin to V
The value of RQ (within 15%) is five times the output impedance desired.
For example, 250
Impedance updates occur early in cycles that do not activate the outputs, such as deselect cycles.
In all cases impedance updates are transparent to the user and do not produce access time "push-outs" or other anomalous
behavior in the SRAM.
To guarantee optimum output driver impedance after power up, the SRAM needs 1024 non-read cycles.
Clock Consideration
K7R643682M
K7R641882M
K7R640982M
To assure the output traceability, the SRAM provides the output Echo clock, pair of compliment clock CQ and CQ,
which are synchronized with internal data output.
Echo clocks run free during normal operation.
The Echo clock is triggered by internal output clock signal, and transferred to external through same structures as output driver.
Ω
DD
resistor will give an output impedance of 50
by more than 0.5V during power-down.
DDQ
does not exceed V
IN
, V
REF
, V
DDQ
DD
2Mx36 & 4Mx18 & 8Mx9 QDR
, V
by more than 0.5V during power-up. The following power-down supply voltage
DD
, V
SS
Ω
- 8 -
. V
.
DD
SS
and V
, V
DD
DDQ
, V
DDQ
can be removed simultaneously, as long as V
, V
REF
, then V
SS
through a precision resistor (RQ).
IN
Rev. 1.3 March 2007
. V
DD
and V
TM
II b2 SRAM
DDQ
can be applied
DDQ