T5743P3 ATMEL [ATMEL Corporation], T5743P3 Datasheet - Page 13

• Manufacturer Part Number: T5743P3
• Description: UHF ASK/FSK Receiver
• Manufacturer: ATMEL [ATMEL Corporation]

Figure 11. Timing Diagram for Complete Successful Bit Check
Bit-check Mode
Configuring the Bit Check
4569A–RKE–12/02
IC_ACTIVE
( Number of checked Bits: 3 )
Bit check
Dem_out
Data_out (DATA)
Start-up mode
T
Start-up
In bit-check mode the incoming data stream is examined to distinguish between a valid
signal from a corresponding transmitter and signals due to noise. This is done by subse-
quent time frame checks where the distances between two signal edges are
continuously compared to a programmable time window. The maximum count of this
edge-to-edge tests before the receiver switches to receiving mode is also
programmable.
Assuming a modulation scheme that contains two edges per bit, two time frame checks
are verifying one bit. This is valid for Manchester, Bi-phase and most other modulation
schemes. The maximum count of bits to be checked can be set to 0, 3, 6 or 9 bits via the
variable N
checks respectively. If N
switch to receiving mode due to noise. In the presence of a valid transmitter signal, the
bit check takes less time if N
time is not dependent on N
successfully and the data signal is transferred to Pin DATA.
According to Figure 12, the time window for the bit check is defined by two separate
time limits. If the edge-to-edge time t
the upper bit-check limit T
T
switches to sleep mode.
Figure 12. Valid Time Window for Bit Check
For best noise immunity it is recommended to use a low span between T
T
preburst. A “11111...” or a “10101...” sequence in Manchester or Bi-phase is a good
choice concerning that advice. A good compromise between receiver sensitivity and
susceptibility to noise is a time window of ±25% regarding the expected edge-to-edge
time t
bit-check limits must be programmed according to the required span.
The bit-check limits are determined by means of the formula below.
Lim_max
Lim_min
ee
. Using pre-burst patterns that contain various edge-to-edge time periods, the
. This is achieved using a fixed frequency at a 50% duty cycle for the transmitter
or t
Bit-check
ee
1/2 Bit
exceeds T
in the OPMODE register. This implies 0, 6, 12 and 18 edge to edge
Dem_out
1/2 Bit
Bit-check mode
Bit-check
T
Lim_max
Bit-check
Bit-check
Lim_max
1/2 Bit
Bit–check
is set to a higher value, the receiver is less likely to
, the bit check will be terminated and the receiver
. Figure 11 shows an example where 3 bits are tested
, the check will be continued. If t
Bit check ok
1/2 Bit
is set to a lower value. In polling mode, the bit-check
ee
T
Lim_min
T
Lim_max
is in between the lower bit-check limit T
t
ee
1/2 Bit
1/f
Sig
1/2 Bit
Receiving mode
ee
is smaller than
T5743
Lim_min
Lim_min
and
and
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