X24641S8-1.8 XICOR [Xicor Inc.], X24641S8-1.8 Datasheet - Page 11

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X24641S8-1.8

Manufacturer Part Number
X24641S8-1.8
Description
400 KHz 2-Wire Serial E 2 PROM
Manufacturer
XICOR [Xicor Inc.]
Datasheet
Bus Timing
X24641
The program cycle time is the time from a valid stop condition of a program sequence to the end of the internal
erase/program cycle. During the program cycle, the X24641 bus interface circuits are disabled, SDA is allowed to
remain HIGH, and the device does not respond to its slave address.
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
Bus Timing
Program Cycle Limits
Notes: (7) Typical values are for T
SDA OUT
SDA
SCL
SDA IN
Symbol
(8) t
T
SCL
WR
120
100
80
60
40
20
time the device requires to automatically complete the nonvolatile write operation.
WR
0
(8)
0
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
MIN.
RESISTANCE
BUS CAPACITANCE (pF)
20
t SU:STA
R MIN =
R MAX =
MAX.
RESISTANCE
40
WORD n
8th BIT
V CC MAX
Program Cycle Time
I OL MIN
C BUS
60
t R
Parameter
A
80 100 120
= 25 C and nominal supply voltage (5V).
=1.8K
t HD:STA
ACK
t F
t AA
7026 FM 16
t HD:DAT
t HIGH
CONDITION
Min.
STOP
11
t LOW
SYMBOL TABLE
t DH
t SU:DAT
WAVEFORM
Typ.
t WR
5
(7)
CONDITION
START
INPUTS
Must be
steady
May change
from Low to
High
May change
from High to
Low
Don’t Care:
Changes
Allowed
N/A
Max.
10
t R
t SU:STO
t BUF
OUTPUTS
Will be
steady
Will change
from Low to
High
Will change
from High to
Low
Changing:
State Not
Known
Center Line
is High
Impedance
Units
ms
7026 FRM T11
7026 FM 17
7026 FM 14
7026 FM 15

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