HM1-6514B-9 INTERSIL [Intersil Corporation], HM1-6514B-9 Datasheet

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HM1-6514B-9

Manufacturer Part Number
HM1-6514B-9
Description
1024 x 4 CMOS RAM
Manufacturer
INTERSIL [Intersil Corporation]
Datasheet
1.HM1-6514B-9.pdf (7 pages)

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
BOSTOCK HK LIMITED BOSTOCK HK LIMITED
Part Number:
HM1-6514B-9
Quantity:
303
March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
Features
• Low Power Standby . . . . . . . . . . . . . . . . . . . 125 W Max
• Low Power Operation . . . . . . . . . . . . . 35mW/MHz Max
• Data Retention . . . . . . . . . . . . . . . . . . . . . . . at 2.0V Min
• TTL Compatible Input/Output
• Common Data Input/Output
• Three-State Output
• Standard JEDEC Pinout
• Fast Access Time. . . . . . . . . . . . . . . . . . 120/200ns Max
• 18 Pin Package for High Density
• On-Chip Address Register
• Gated Inputs - No Pull Up or Pull Down Resistors
Ordering Information
Pinouts
HM3-6514S-9
HM1-6514S-9
24502BVA
8102402VA
Required
120ns
GND
A6
A5
A4
A3
A0
A1
A2
HM-6514 (PDIP, CERDIP)
-
-
E
1
2
3
4
5
6
7
8
9
TOP VIEW
HM3-6514B-9
HM1-6514B-9
8102404VA
200ns
18
17
16
15
14
13
12
11
10
|
-
-
-
Copyright
V
A7
A8
A9
DQ0
DQ1
DQ2
DQ3
W
CC
©
Intersil Corporation 1999
HM3-6514-9
HM1-6514-9
8102406VA
HM4-6514-B
300ns
PIN
-
-
W
Q
A
E
D
Address Input
Chip Enable
Write Enable
Data Input
Data Output
6-1
DESCRIPTION
TEMPERATURE RANGE
Description
The HM-6514 is a 1024 x 4 static CMOS RAM fabricated
using self-aligned silicon gate technology. The device utilizes
synchronous circuitry to achieve high performance and low
power operation.
On-chip latches are provided for addresses allowing efficient
interfacing with microprocessor systems. The data output
can be forced to a high impedance state for use in expanded
memory arrays.
Gated inputs allow lower operating current and also elimi-
nate the need for pull up or pull down resistors. The
HM-6514 is a fully static RAM and may be maintained in any
state for an indefinite period of time.
Data retention supply voltage and supply current are guaran-
teed over temperature.
-55
-40
-40
-40
o
o
o
o
C to +125
C to +85
C to +85
C to +85
-
-
o
o
o
o
C
C
C
C
HM-6514
A4
A3
A0
A1
A2
PDIP
CERDIP
CLCC
JAN#
SMD#
PACKAGE
3
4
5
6
7
1024 x 4 CMOS RAM
HM-6514 (CLCC)
2
8
TOP VIEW
9
1
File Number
10
18
E18.3
F18.3
F18.3
F18.3
J18.B
J18.B
11
17
PKG. NO.
16
15
14
13
12
A8
A9
DQ0
DQ1
DQ2
2995.1

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HM1-6514B-9 Summary of contents

Page 1

... Fast Access Time 120/200ns Max • 18 Pin Package for High Density • On-Chip Address Register • Gated Inputs - No Pull Up or Pull Down Resistors Required Ordering Information 120ns 200ns HM3-6514S-9 HM3-6514B-9 HM1-6514S-9 HM1-6514B-9 24502BVA - 8102402VA 8102404VA - - - - Pinouts HM-6514 (PDIP, CERDIP) TOP VIEW ...

Page 2

Functional Diagram LSB LSB HM-6514 A 6 LATCHED GATED ADDRESS ROW 64 MATRIX A REGISTER DECODER ...

Page 3

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

AC Electrical Specifications V CC SYMBOL PARAMETER (1) TELQV Chip Enable Access Time (2) TAVQV Address Access Time (3) TELQX Chip Enable Output Enable Time (4) TEHQZ Chip Enable Output Disable Time (5) TELEH Chip Enable Pulse Negative Width (6) ...

Page 5

Timing Waveforms (7) TAVEL A VALID ADD (6) TEHEL E HIGH TIME REFERENCE -1 0 INPUTS TIME REFERENCE The address information is latched in the ...

Page 6

Timing Waveforms (Continued) TAVEL A VALID ADD TEHEL E W HIGH Z DQ TIME REFERENCE -1 INPUTS TIME REFERENCE The write cycle is initiated by the falling edge ...

Page 7

Test Load Circuit DUT (NOTE 1) C NOTE: 1. Test head capacitance. All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification. Intersil products are sold by description only. Intersil Corporation reserves the right to make ...

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