K9K1G08U0A Samsung semiconductor, K9K1G08U0A Datasheet - Page 13

• Manufacturer Part Number: K9K1G08U0A
• Description: 128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
• Manufacturer: Samsung semiconductor

Valid Block
NOTE :
1. The
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
3.
AC TEST CONDITION
(K9K1GXXX0A-XCB0 :TA=0 to 70 C, K9K1GXXX0A-XIB0 :TA=-40 to 85 C
Capacitance
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
NOTE : 1. X can be V
Program / Erase Characteristics
K9K1G08Q0A
K9K1G08U0A
K9K1GXXQ0A : Vcc=1.70V~1.95V , K9K1GXXU0A : Vcc=2.7V~3.6V unless otherwise noted)
Valid Block Number
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
K9K1GXXQ0A:Output Load (Vcc
K9K1GXXU0A:Output Load (Vcc
K9K1GXXU0A:Output Load (Vcc
Input/Output Capacitance
Input Capacitance
Program Time
Dummy Busy Time for Multi Plane Program
Number of Partial Program Cycles
in the Same Page
Block Erase Time
sented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits
these invalid blocks for program and erase.
Minimum 1004 valid blocks are guaranteed for each contiguous 128Mb memory space.
CLE
H
H
X
X
X
X
X
L
L
L
L
L
device
2. WP should be biased to CMOS high or CMOS low for standby.
Parameter
ALE
may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is pre-
X
H
H
L
L
L
L
L
X
X
X
X
Item
(1)
(
T
IL
Parameter
A
or V
=25 C, V
CE
X
X
X
X
H
L
L
L
L
L
L
L
IH.
Parameter
K9K1G16Q0A
K9K1G16U0A
WE
CC
H
H
X
X
X
X
X
Q
Q
Q
=1.8V/3.3V, f=1.0MHz)
:3.0V +/-10%)
:3.3V +/-10%)
:1.8V +/-10%)
RE
Symbol
Symbol
H
H
H
H
H
H
H
X
X
X
X
N
C
C
VB
I/O
IN
Spare Array
Main Array
Refer to the attached technical notes for an appropriate management of invalid blocks.
GND
0V
X
X
X
X
X
X
L
L
L
L
L
Test Condition
WP
0V/
1 TTL GATE and CL=30pF
H
H
H
H
H
X
X
X
X
X
L
V
V
8,042
IN
IL
Min
Symbol
=0V
=0V
During Read(Busy) on K9K1G08U0A_Y,P or K9K1G08U0A_V,F
During Read(Busy) on the devices except K9K1G08U0A_Y,P and
K9K1G08U0A_V,F
t
t
t
K9K1GXXQ0A
Data Input
Data Output
During Program(Busy)
During Erase(Busy)
Write Protect
Stand-by
PROG
DBSY
Nop
BERS
13
0V to Vcc
Read Mode
Write Mode
Vcc
5ns
-
Q
/2
Q
Min
-
-
-
-
Typ.
Min
Command Input
Address Input(4clock)
Command Input
Address Input(4clock)
-
-
-
Typ
200
Mode
1
2
-
-
FLASH MEMORY
1 TTL GATE and CL=100pF
1 TTL GATE and CL=50pF
8,192
Max
Max
20
20
K9K1GXXU0A
0.4V to 2.4V
Max
500
10
1.5V
1
2
3
5ns
Preliminary
. Do not try to access
Blocks
Unit
Unit
pF
pF
cycles
cycle
Unit
ms
s
s