K9K1G08U0A Samsung semiconductor, K9K1G08U0A Datasheet - Page 34

• Manufacturer Part Number: K9K1G08U0A
• Description: 128M x 8 Bit / 64M x 16 Bit NAND Flash Memory
• Manufacturer: Samsung semiconductor

BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase
Setup command(60h). Only address A
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 14 details the sequence.
Figure 14. Block Erase Operation
Multi-Plane Page Program into Plane 0~3 or Plane 4~7
Multi-Plane Page Program is an extension of Page Program, which is executed for a single plane with 528 byte page registers. Since
the device is equipped with eight memory planes, activating the four sets of 528 byte page registers into plane 0~3 or plane 4~7
enables a simultaneous programming of four pages. Partial activation of four planes is also permitted.
After writing the first set of data up to 528 byte into the selected page register, Dummy Page Program command (11h) instead of
actual Page Program (10h) is inputted to finish data-loading of the current plane and move to the next plane. Since no programming
process is involved, R/B remains in Busy state for a short period of time(tDBSY). Read Status command (standard 70h or alternate
71h) may be issued to find out when the device returns to Ready state by polling the Ready/Busy status bit(I/O 6). Then the next set
of data for one of the other planes is inputted with the same command and address sequences. After inputting data for the last plane,
actual True Page Program (10h) instead of dummy Page Program command (11h) must be followed to start the programming pro-
cess. The operation of R/B and Read Status is the same as that of Page Program. Since maximum four pages into plane 0~3 or plane
4~7 are programmed simultaneously, pass/fail status is available for each page when the program operation completes. The
extended status bits (I/O1 through I/O 4) are checked by inputting the Read Multi-Plane Status Register. Status bit of I/O 0 is set to "1"
when any of the pages fails.
Multi-Plane page Program with "01h" pointer is not supported, thus prohibited.
Figure 15. Four-Plane Page Program
R/B
I/O
K9K1G08Q0A
K9K1G08U0A
R/B
I/O
Data
input
0
0
~
~
7
7
80h
80h
A
60h
0
528 Byte Data
Data Input
~ A
Block 4092
Address &
Block 4088
Plane 0
(1024 Block)
Block 0
Block 4
7
& A
K9K1G16Q0A
K9K1G16U0A
9
~ A
Address Input(3Cycle)
Block Add. : A
26
11h
11h
t
DBSY
14
80h
14
80h
to A
~ A
A
0
26
528 Byte Data
26
~ A
Data Input
Address &
is valid while A
Plane 1
(1024 Block)
Block 4093
Block 4089
7
Block 1
Block 5
& A
9
D0h
~ A
26
11h
11h
t
9
DBSY
to A
34
13
t
80h
80h
BERS
is ignored. The Erase Confirm command(D0h) following the
A
0
528 Byte Data
~ A
Data Input
Address &
Block 4094
Block 4090
Plane 2
(1024 Block)
7
Block 2
Block 6
& A
9
~ A
26
70h
11h
11h
t
DBSY
FLASH MEMORY
80h
80h
A
0
528 Byte Data
~ A
Data Input
Address &
Plane 3
(1024 Block)
Block 4095
Block 4091
7
Block 3
Block 7
& A
Preliminary
9
I/O
Fail
~ A
0
26
10h
10h
t
PROG
Pass
71h