PLS159 PHILIPS [NXP Semiconductors], PLS159 Datasheet - Page 6

• Manufacturer Part Number: PLS159
• Manufacturer: PHILIPS [NXP Semiconductors]

1. All typical values are at V
2. To prevent spurious clocking, clock rise time (10% – 90%)
3. For 3-State output; output enable times are tested with C
4. When using the Complement Array t
5. Limits are guaranteed with 12 product terms maximum connected to each sum term line.
Philips Semiconductors Programmable Logic Devices
AC ELECTRICAL CHARACTERISTICS
0 C
NOTES:
VOLTAGE WAVEFORMS
October 22, 1993
+3.0V
+3.0V
SYMBOL
MEASUREMENTS:
All circuit delays are measured at the +1.5V level
of inputs and outputs, unless otherwise specified.
Programmable logic sequencer
(16
Pulse width
t
t
t
t
Setup time
t
t
t
Hold time
t
t
Propagation delay
t
t
t
t
t
t
t
t
closed for high-impedance to Low tests. Output disable times are tested with C
voltage of V
CKH
CKL
CKP
PRH
IS1
IS2
IS3
IH1
IH2
CKO
OE1
OD1
PD
OE2
OD2
PRO
PPR
0V
0V
T
amb
45
5ns
+75 C, 4.75V
5ns
5
T
Clock
Clock Low
Period
Preset/Reset pulse
Input
Input (through F
Input (through
Complement Array)
Input
Input (through F
Clock
Output enable
Output disable
Output
Output enable
Output disable
Preset/Reset
Power-on/preset
= (V
Input Pulses
OH
12)
2
t
R
High
PARAMETER
– 0.5V) with S
t
F
10%
CC
V
3
3
3
3
CC
= 5V, T
n
n
)
)
5ns
5ns
4
5.25V, R
90%
1
amb
CKP
10%
open, and Low-to-High impedance tests are made to the V
90%
= +25 C.
= 75ns (min).
1
=470 , R
TEST LOAD CIRCUIT
NOTE:
C
FROM
(I,B) –
(I,B)
(I,B)
(I,B)
(I,B)
(I,B) +
(I,B) –
(I,B) +
V
1
CK +
CK –
CK +
CK +
OE –
OE +
F
F
CC
and C
2
= 1k
+
C
1
2
L
are to bypass V
= 30pF to the 1.5V level, and S
10ns.
(I,B) +
CK –
CK +
CK +
CK +
CK +
CK +
CK +
CK +
F +
B
B
B +
TO
F
F –
F
F –
30
C
CC
2
INPUTS
to GND.
TEST CONDITION
L
= 5pF. High-to-High impedance tests are made to an output
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
C
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
= 30pF
= 30pF
= 30pF
= 30pF
= 30pF
= 30pF
= 30pF
= 30pF
= 30pF
= 30pF
= 30pF
= 30pF
= 30pF
= 30pF
= 30pF
= 5pF
= 5pF
B
1
CLK
B
I
I
n
0
W
X
is open for high-impedance to High tests and
V
CC
GND
T
DUT
= (V
OL
+5V
OE
B
B
MIN
20
20
55
35
35
15
55
15
Y
Z
0
+ 0.5V) level with S
S
LIMITS
OUTPUTS
1
TYP
15
15
45
30
30
10
45
–5
10
15
20
20
25
20
20
35
0
1
R
2
Product specification
PLS159A
MAX
20
30
30
35
30
30
45
10
R
1
1
closed.
C
L
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns