HCMS-235x Hewlett-Packard, HCMS-235x Datasheet - Page 5

• Manufacturer Part Number: HCMS-235x
• Description: CMOS Extended Temperature Range 5 x 7 Alphanumeric Display
• Manufacturer: Hewlett-Packard

5
Electrical Description
The display contains four 5 x 7
LED dot matrix characters and
two CMOS integrated circuits,
as shown in Figure 1. The two
CMOS integrated circuits form
an on-board 28 bit serial-in/
parallel-out shift register that
will accept standard TTL logic
levels. The Data Input, pin 12,
is connected to bit position 1
and the Data Output, pin 7, is
connected to bit position 28.
The shift register outputs
control constant current sinking
LED row drivers. A logic 1
stored in the shift register
enables the corresponding LED
row driver and a logic 0 stored
in the shift register disables the
corresponding LED row driver.
Figure 1. Display block diagram.
BLANKING
CONTROL, V
SERIAL
DATA
INPUT
B
1 2 3 4 5
1
2 3 4 5 6 7
CLOCK
ROWS
6 7
COLUMN DRIVE INPUTS
1 2 3 4 5
COLUMN
The electrical configuration of
these CMOS IC alphanumeric
displays allows for an effective
interface to a display controller
circuit that supplies decoded
character information. The row
data for a given column (one 7
bit byte per character) is loaded
(bit serial) into the on-board 28
bit shift register with high to
low transitions of the Clock
input. To load decoded
character information into the
display, column data for
character 4 is loaded first and
the column data for character 1
is loaded last in the following
manner. The 7 data bits for
column 1, character 4, are
loaded into the on-board shift
register. Next, the 7 data bits
for column 1, character 3, are
loaded into the shift register,
CONSTANT CURRENT SINKING LED DRIVERS
28-BIT SIPO SHIFT REGISTER
ROWS 8-14
ROWS 1-7
MATRIX
LED
2
ROWS 15-21
ROWS 1-7
MATRIX
LED
3
shifting the character 4 data
over one character position.
This process is repeated for the
other two characters until all 28
bits of column data (four 7 bit
bytes of character column data)
are loaded into the on-board
shift register. Then the column
1 input, V
energized to illuminate column
1 in all four characters. This
process is repeated for columns
2, 3, 4 and 5. All V
should be at logic low to insure
the display is off when loading
data. The display will be
blanked when the blanking
input V
regardless of the outputs of the
shift register or whether one of
the V
Refer to Application Note 1016
for drive circuit information.
COL
B
ROWS 22-28
, pin 8, is at logic low
ROWS 1-7
inputs is energized.
COL
MATRIX
pin 1, is
LED
4
COL
inputs
SERIAL
DATA
OUTPUT