LS7212N LSI [LSI Computer Systems], LS7212N Datasheet
LS7212N
Related parts for LS7212N
LS7212N Summary of contents
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... LS7211N, LS7212N (DIP); LS7211N-S, LS7212N-S (SOIC) - See Figure 1 - DESCRIPTION: The LS7211N and LS7212N are CMOS integrated circuits for generating digitally programmable delays. The delay is con- trolled by 8 binary weighted inputs, WB0 - WB7, in conjunction with an applied clock or oscillator frequency. The programmed ...
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... RCS/CLKS input (Pin 5); the internal oscillator mode is selected by applying a high level to the RCS/CLKS input. LS7212N TIME BASE Input (XTLI/CLOCK, Pin 4) For LS7212N, the basic timing clock is applied to the XLTI/ CLOCK input from either an external clock source or gener- ated by an internal crystal oscillator by connecting a crystal between XTLI/CLOCK input and the XTLO output (Pin 5) ...
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ABSOLUTE MAXIMUM RATINGS: (All voltages referenced Supply Voltage Voltage (Any Pin) Operating Temperature Storage Temperature ELECTRICAL CHARACTERISTICS (Voltages referenced to Vss) Characteristic SYMBOL Supply Voltage V DD Supply Current I DD Input Voltages: Reset, Trigger Low V ...
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... TRIG Set-Up Time A, B Set-Up Time WB0 - WB7 Set-Up Time Clock to Out Delay +V 500k 500k B 2 TRIG 18 500k RESET 7 4 CLOCK/RC/XTLI OSC XTLO (LS7212N RCS/CLKS (LS7211N) 500k +V PSCLS 6 FIGURE 2. LS7211N / LS7212N BLOCK DIAGRAM 7211N-072009 Min Max Min 3 10.0 - 4.5 - osc 18.0 - 8.0 - 3 ...
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Clock t 1 TRIG Delayed Operate WB0-WB7 OUT Note 1. TRIG input is clocked in by the negative edge of external clock. Note 2. Inputs A, ...
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... FIGURE 6. MULTI-TIMER WITH SINGLE CRYSTAL TIME-BASE 8 = 1kHz 120VAC FIGURE 7. DRIVING CLOCK INPUT FROM THE AC LINE + OUT Vss 8 470k 5 XTLO LS7212N 10M 4 XTLI + V LS7211N 1M 4 CLOCK 200pF 10- WB0-WB7 LS7211N 18 TRIG OUT 4 CLOCK Vss 8 LS7211N 4 CLOCK 4 CLOCK LS7212N OUT ...
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... OUTPUT NOTE : Crystal Frequency, ƒ = 32,768Hz FIGURE 9. PROGRAMMABLE ACCURATE REAL-TIME DELAY GENERATION 7211N-052606 TRIG 4 XTLI 10M 5 XTLO 6 PSCLS LS7212N 7 RESET 8 Vss 9 OUT Switch: S1 low: Delay increment = 1s; Maximum Delay = 255s S1 high: Delay increment = 1m; Maximum Delay = 255m + 1s/1m 17 WB0 2s/2m 16 WB1 ...
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... Case 1, Mode = DO; 4 ƒo ÷ Case 2, Mode = DD; 6 FIGURE 10. PROGRAMMABLE FREQUENCY DIVIDER 7211N-052606 CLOCK LS7212N 7 RESET 18 TRIG 9 OUT Vss 8 ƒi ƒo = where W (weighting factor 255 ƒi where W (weighting factor 255 ƒ WB0 ...