LS7212N LSI [LSI Computer Systems], LS7212N Datasheet - Page 8

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LS7212N

Manufacturer Part Number
LS7212N
Description
PROGRAMMABLE DIGITAL DELAY TIMER
Manufacturer
LSI [LSI Computer Systems]
Datasheet
7211N-052606-8
ƒo
Case 1, Mode = DO;
ƒo
Case 2, Mode = DD;
EXAMPLES OF CASE 1 and CASE 2 FREQUENCY DIVISIONS WITH W = 2
CASE 1. MODE = DO or DR; PRESCALE FACTOR, S = 1
CASE 2. MODE = DD; PRESCALE FACTOR, S = 1
ƒi
In this setup a frequency division of the input clock, ƒi by a factor of 2 to 257, in increments of 1 can
be obtained according to the equation:
The ƒo pulse widths are symmetrical with 50% duty -cycle
The ƒo pulse width is non-symmetrical (non-50% duty -cycle)
In this setup a frequency division of the input clock, ƒi by a factor of 2 to 512, in increments of 2 can
be obtained according to the equation:
ƒo
+V
÷
÷
ƒi
FIGURE 10. PROGRAMMABLE FREQUENCY DIVIDER
6
4
ƒo =
ƒo =
W + 2
18
2 (W + 1)
ƒi
2
1
4
9
7
ƒi
A
B
RESET
OUT
CLOCK
TRIG
where W (weighting factor) = 0 to 255
where W (weighting factor) = 0 to 255
LS7212N
3
V
+V
Vss
DD
8
WB3
WB7
WB0
WB1
WB2
WB4
WB5
WB6
17
16
15
14
13
12
11
10

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