CMX625P4 CMLMICRO [CML Microcircuits], CMX625P4 Datasheet - Page 14

• Manufacturer Part Number: CMX625P4
• Description: ISDN TA POTS Interface
• Manufacturer: CMLMICRO [CML Microcircuits]

ISDN TA POTS Interface
In Terminal mode (TE) it may also be necessary to transmit on the Data Downstream (DD) pin and receive
on the Data Upstream (DU) pin during the IC1 and IC2 time slots. This can be achieved by selecting bus
reversal and allows use of the CMX625 with post processing devices, such as speech scramblers, that are
IOM-2 compliant. Bus Reversal is enabled when bit 4 of the IOM Control Register is set to ‘1’ and
programming the appropriate Codec Channel Select bits 6 and 7 of the IOM Control Register. When bus
reversal is active, the master device and any other devices capable of bus reversal, are prohibited from
broadcasting in the active IC channel.
Local analogue codec loopback is enabled when bit 5 of the CODEC CONTROL Register is set to ‘1’.
This internally connects the DAC output to the ADC input (the connection to the Rx Amp is broken). Data
is loaded and read via the IOM-2 bus using the channels shown in the above table.
1.5.7
This amplifier, with suitable external components, is used for adjusting the received signal to the correct
amplitude for the DTMF decoder and the PCM analogue-to-digital converter. See Figure 2 Recommended
External Components.
1.5.8
This buffer is enabled by bit 7 of the SETUP register. With suitable external components it can be used
for filtering and impedance matching. See Figure 2 Recommended External Components.
1.5.9
These blocks are enabled or disabled by bit 6 of the SETUP register. When bit 5 of the MODE Register is
set to ‘1’ then these blocks generate FSK signals as determined by bit 0 of the SETUP Register and the Tx
data bits from the UART block, as shown in the table below:
When bit 5 of the MODE Register is set to ‘0’, these blocks generate single or dual tones from the range
shown in the tables on the following pages. Bit 6 of the MODE Register is then used to enable or disable
the block’s output to the Tx Signal Control, RING and TONEFSK outputs. There are four tone fields
addressed by bits 0 and 1 of the MODE Register.
SETUP Register
2001 Consumer Microcircuits Limited
Bit 0
Rx Input Amplifier
Tx Output Buffer
Tone/FSK Encoder and Tone Encoder
0
1
IC Channel Bus Reversal
Reverse
(IOM Control Register
Normal
Bell 202 1200bps FSK
Bit 4)
Tone/FSK Generator
V23 1200bps FSK
0
0
0
1
1
1
0
1
Codec Channel Input/Output Select
(IOM Control Register,
Codec Channel Select
Bits 7 and 6)
0 0
0 1
1 0
1 1
0 0
0 1
1 0
1 1
14
FSK Signal Frequency
‘0’ (Space)
2100Hz
2200Hz
IC1, DD
IC2, DD
IC1, DU
IC2, DU
B1, DD
B2, DD
B1, DD
B2, DD
Codec
From
Data
FSK Signal Frequency
IC1, DU
IC2, DU
IC1, DD
IC2, DD
B1, DU
B2, DU
B1, DU
B2, DU
Codec
Data
To
‘1’ (Mark)
1300Hz
1200Hz
CMX625
D/625/2