CMX625P4 CMLMICRO [CML Microcircuits], CMX625P4 Datasheet - Page 18

• Manufacturer Part Number: CMX625P4
• Description: ISDN TA POTS Interface
• Manufacturer: CMLMICRO [CML Microcircuits]

ISDN TA POTS Interface
1.5.12 Tx UART
This block connects the IOM-2 serial bus interface to the FSK Encoder.
The block can be programmed to convert transmit data from 8-bit bytes to asynchronous data characters
by adding Start and Stop bits. The transmit data is then passed to the FSK Encoder.
Data to be transmitted should be loaded, via the IOM-2 bus interface, into the TX DATA Register when the
Tx Data Ready bit (bit 6) of the STATUS Register goes high. It will then be treated by the Tx UART block
in one of two ways, depending on the setting of bit 1 of the SETUP Register:
Failure to load the TX DATA Register with a new value when required will result in bit 7 (Tx Data
Underflow) of the STATUS Register being set to ‘1’. If the ‘Tx Async’ mode of operation is selected then a
continuous Mark (‘1’) signal will be transmitted until a new value is loaded into TX DATA. If the ‘Tx Sync’
mode is selected then the byte already in the TX DATA Register will be re-transmitted.
2001 Consumer Microcircuits Limited
If bit 1 of the SETUP Register is ‘0’ (Tx Sync mode) then the 8 bits from the TX DATA Register will
be transmitted sequentially at 1200bps, lsb (D0) first.
If bit 1 of the SETUP Register is ‘1’ (Tx Async mode) then bits will be transmitted as asynchronous
data characters at 1200 bps according to the following format:
One Start bit (Space)
Eight Data bits (D0-D7) from the TX DATA Register, with the lsb (D0) transmitted first
One Stop bit (Mark)
Figure 9a Transmit UART Function (Async)
Figure 9b Transmit UART Function (Sync)
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