CMX625P4 CMLMICRO [CML Microcircuits], CMX625P4 Datasheet - Page 30

• Manufacturer Part Number: CMX625P4
• Description: ISDN TA POTS Interface
• Manufacturer: CMLMICRO [CML Microcircuits]

ISDN TA POTS Interface
Notes:
Tx Output Buffer
Buffer output signal swing;
Power-Up Timing
Device reset to reliable signal at TXO, TXON,
RING, SPM or TONEFSK output pins
2001 Consumer Microcircuits Limited
Load greater than 500
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Over the range V
11. Represents a psophometrically weighted measurement.
12. For each of the TXON (if enabled) and TXO pins, load placed between the pin and
13. Derate linearly minimum TTL Logic ‘0’ level from 0.8V at Vdd = 3.3V to 0.5V at
14. All outputs CMOS levels.
Frequency above 300Hz.
At 25 C, not including any current drawn from the CMX625 pins by external circuitry.
At nominal signal frequencies and without skew.
Excluding IOM-2 serial bus interface pins: FSC, DCL, DD and DU in bus reversal.
At V
Referenced to DTMF tone of lower amplitude.
Bandwidth limited: 0 to 3.4kHz Gaussian Noise.
See filter response, Figure 12.
SPM has a soft rise and fall time of about 4ms. The level changes between V
0dBm in 2dB steps, 16 steps per rise and fall. When SPM is disabled, an extra 4ms
falling tail end of signal should be taken into consideration.
V
Vdd = 2.7V.
DD
DD
/ 2, for V
= 5.0V, load resistance greater than 40k , signal levels are proportional to V
DD
= 5.0V only.
DD
= 3.3V to 5.5V at Tamb = 25°C.
30
Notes
Notes
12
Min.
Min.
2.2
-
Typ.
Typ.
50.0
-
Max.
Max.
-
-
BIAS
CMX625
D/625/2
and
Vp-p
DD
Unit
Unit
ms
.