L8C201JC10 LODEV [LOGIC Devices Incorporated], L8C201JC10 Datasheet - Page 14

• Manufacturer Part Number: L8C201JC10
• Description: 512/1K/2K/4K x 9-bit Asynchronous FIFO
• Manufacturer: LODEV [LOGIC Devices Incorporated]

DEVICES INCORPORATED
1. Maximum Ratings indicate stress specifi-
cations only. Functional operation of these
products at values beyond those indicated
in the Operating Conditions table is not
implied. Exposure to maximum rating con-
ditions for extended periods may affect re-
liability of the tested device.
2. The products described by this specifica-
tion include internal circuitry designed to
protect the chip from damaging substrate
injection currents and accumulations of
static charge. Nevertheless, conventional
precautions should be observed during
storage, handling, and use of these circuits
in order to avoid exposure to excessive elec-
trical stress values.
3. This product provides hard clamping of
transient undershoot. Input levels below
ground will be clamped beginning at –0.6 V.
A current in excess of 100 mA is required to
reach –2 V. The device can withstand in-
definite operation with inputs as low as –3 V
subject only to power dissipation and bond
wire fusing constraints.
4. “Typical” supply current values are not
shown but may be approximated. At a V
of +5.0 V, an ambient temperature of +25°C
and with nominal manufacturing parame-
ters, the operating supply currents will be
approximately 3/4 or less of the maximum
values shown.
5. Tested with outputs open and data in-
puts changing at the specified read and
write cycle rate. The device is neither full or
empty for the test.
6. Tested with outputs open in the worst
static input control signal combination (i.e.,
W, R, XI, FL, and RS).
7. These parameters are guaranteed but not
100% tested.
8. Test conditions assume input transition
times of 5 ns or less, reference levels of 1.5 V,
output loading for specified I
plus 30 pF (Fig. 2a), and input pulse levels of
0 to 3.0 V (Fig. 3).
9. Each parameter is shown as a minimum
or maximum value. Input requirements are
specified from the point of view of the exter-
nal system driving the chip. For example,
t
external system must supply at least that
much time to meet the worst-case require-
RLRH
NOTES
is specified as a minimum since the
OL
and I
OH
CC
ments of all parts. Responses from the inter-
nal circuitry are specified from the point of
view of the device. Access time, for ex-
ample, is specified as a maximum since
worst-case operation of any device always
provides data within that time.
10. When cascading devices, the reset pulse
width must be increased to equal t
t
11. It is not recommended that Logic De-
vices and other vendor parts be cascaded
together. The parts are designed to be pin-
for-pin compatible but temperature and
voltage compensation may vary from ven-
dor to vendor. Logic Devices can only guar-
antee the cascading of Logic Devices parts to
other Logic Devices parts.
12. Tested with output open and RS = FL
= XI = R = W = V
13. At any given temperature and voltage
condition, output disable time is less than
output enable time for any given device.
14. Transition is measured ±200 mV from
steady state voltage with specified loading
in Fig. 2b. This parameter is sampled and
not 100% tested.
15. This product is a very high speed device
and care must be taken during testing in
order to realize valid test information. Inad-
equate attention to setups and procedures
can cause a good part to be rejected as faulty.
Long high-inductance leads that cause sup-
ply bounce must be avoided by bringing the
V
contactor fingers. A 0.01 µF high frequency
capacitor is also required between V
ground. To avoid signal reflections, proper
terminations must be used.
SLHH
CC
and ground planes directly up to the
.
CC
.
512/1K/2K/4K x 9-bit Asynchronous FIFO
14
CC
SLSH
and
+
F
F
F
OUTPUT
OUTPUT
GND
+3.0 V
IGURE
IGURE
IGURE
+5 V
+5 V
<3 ns
INCLUDING
JIG AND
SCOPE
INCLUDING
JIG AND
SCOPE
2a.
2b.
3.
10%
L8C201/202/203/204
90%
FIFO Products
03/04/99–LDS.8C201/2/3/4-H
R
R
5 pF
30 pF
1
1
480
480
90%
10%
R
255
R
255
<3 ns
2
2