AX88796LF ASIX Electronics, AX88796LF Datasheet - Page 26

no-image

AX88796LF

Manufacturer Part Number
AX88796LF
Description
3-in-1 Local CPU Bus Fast Rthernet Controller
Manufacturer
ASIX Electronics
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AX88796LF
Manufacturer:
ASIX
Quantity:
15
Part Number:
AX88796LF
Manufacturer:
ASIX
Quantity:
20 000
TRANSMISSION
Prior to transmission, the TPSR (Transmit Page Start Register) and TBCR0, TBCR1 (Transmit Byte Count
Registers) must be initialized. To initiate transmission of the packet the TXP bit in the Command Register is set.
The Transmit Status Register (TSR) is cleared and the AX88796 begins to prefetch transmit data from memory.
If the Interpacket Gap (IPG) has timed out the AX88796 will begin transmission.
CONDITIONS REQUIRED TO BEGIN TRANSMISSION
In order to transmit a packet, the following three conditions must be met:
1. The Interpacket Gap Timer has timed out
2. At least one byte has entered the FIFO. (This indicates that the burst transfer has been started)
3. If a collision had been detected then before transmission the packet backoff time must have timed out.
COLLISION RECOVERY
During transmission, the Buffer Management logic monitors the transmit circuitry to determine if a collision has
occurred. If a collision is detected, the Buffer Management logic will reset the FIFO and restore the Transmit
DMA pointers for retransmission of the packet. The COL bit will be set in the TSR and the NCR (Number of
Collisions Register) will be incremented. If 15 retransmissions each result in a collision the transmission will be
aborted and the ABT bit in the TSR will be set.
Transmit Packet Assembly Format
The following diagrams describe the format for how packets must be assembled prior to transmission for
different byte ordering schemes. The various formats are selected in the Data Configuration Register and setting
the
CPU[1:0]
AX88796 L
pins for ISA, 80186, MC68K or MCS-51 mode.
General Transmit Packet Format
D15
BOS = 0, WTS = 1 in Data Configuration Register.
This format is used with ISA or 80186 Mode.
Destination Address
Source Address
Length / Type
Data
(Pad if < 46 Bytes)
Destination Address 1
Destination Address 3
Destination Address 5
Source Address 1
Source Address 3
Source Address 5
Type / Length 1
Data 1
3-in-1 Local Bus Fast Ethernet Controller
D8 D7
6 Bytes
6 Bytes
2 Bytes
46 Bytes
Min.
26
Destination Address 0
Destination Address 2
Destination Address 4
Source Address 0
Source Address 2
Source Address 4
Type / Length 0
Data 0
ASIX ELECTRONICS CORPORATION
D0

Related parts for AX88796LF